Title:
DEFECT ANALYSIS MEMORY FOR MEMORY TESTER
Document Type and Number:
WIPO Patent Application WO/1998/020498
Kind Code:
A1
Abstract:
A defect analysis memory for a memory tester comprising a fail data storage unit which has a fail data memory and a 1st memory control part and a mask data storage unit which has a mask data memory and a 2nd memory control part. The 1st memory control part generates a write enable signal to write fail data into an address corresponding to the fail data memory if the logic comparison result of the memory tester shows a defect in a test mode and reads the fail data from the fail data memory and supplies them to the mask data storage unit in a remove mode. The 2nd memory control part supplies mask data which are read from the mask data memory to the logic comparator of the memory tester as a prohibition signal to prohibit the logic comparison in the test mode and generates a write enable signal from the fail data which are read from the fail data memory and supplies the signal to the mask data memory to write the mask data into the corresponding address in the remove mode.
Inventors:
TABATA MAKOTO (JP)
SATO SHINYA (JP)
SATO SHINYA (JP)
Application Number:
PCT/JP1997/003928
Publication Date:
May 14, 1998
Filing Date:
October 29, 1997
Export Citation:
Assignee:
ADVANTEST CORP (JP)
TABATA MAKOTO (JP)
SATO SHINYA (JP)
TABATA MAKOTO (JP)
SATO SHINYA (JP)
International Classes:
G01R31/28; G01R31/3193; G11C29/44; G11C29/56; G06F11/22; (IPC1-7): G11C29/00
Foreign References:
| JPS5528118A | 1980-02-28 | |||
| JPH04318398A | 1992-11-09 | |||
| JPH05242695A | 1993-09-21 | |||
| JPH07130199A | 1995-05-19 |
Attorney, Agent or Firm:
Kusano, Takashi (2-21 Shinjuku 4-chom, Shinjuku-ku Tokyo 160, JP)
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