GIMELSHEIN NATALIA (US)
JOHNSEN THOR MIKAL (US)
LAYTON SIMON (US)
US20190138934A1 | 2019-05-09 |
CLAIMS WHAT IS CLAIMED IS: 1. A processor comprising: two or more processing cores to train portions of a neural network separately in parallel. 2. A processor of claim 1, wherein the two or more processing cores apply one or more gradients to different sets of nodes of the neural network. 3. The processor of claim 1, where in the neural network is trained, at least in part, by generating a weight update by combining a plurality of a partial weight updates produced in parallel by the two or more processing cores. 4. The processor of claim 1, wherein the processor further divides a weight update operation into a plurality of partial weight update operations and distributes individual partial weight update operations to the two or more processing cores. 5. The processor of claim 4, wherein the partial weight update operations are produced by dividing an initial weight and gradient update into a plurality of distinct portions. 6. The processor of claim 4, wherein each partial weight update is executed using a different thread. 7. The processor of claim 4, wherein the processor further gathers the partial weight updates to produce the weight update. 8. A system, comprising: one or more processors to train portions of a neural network separately in parallel; and one or more memories to store the neural network. 9. The system of claim 8 where in the neural network is trained, at least in part, by: generating a plurality of partial weight updates in parallel using the one or more processors; and combining the plurality of partial weight updates to produce a weight gradient update. 10. The system of claim 9, wherein the plurality of partial weight updates is produced in parallel using a plurality of worker threads. 11. The system of claim 9, wherein the neural network is trained at least in part by: forwarding propagating an input through the neural network to produce an output; determining an error based at least in part on a difference between the output and an expected value; and backpropagating the error to determine a gradient, the plurality of partial weight updates based at least in part on the gradient. 12. The system of claim 9, wherein the plurality of partial weight updates are produced at least by: identifying a plurality of subsets of network nodes of the neural network; and producing a partial weight update for each subset in the plurality of subsets. 13. The system of claim 12, wherein the plurality of subsets are non-overlapping subsets of weights of the neural network. 14. The system of claim 12, wherein: an individual subset of the plurality of subsets includes a quantity of node weights; and the quantity of node weights is determined based at least in part on an amount of processing power available to a worker assigned to process the individual subset relative to other workers assigned to process other subsets. 15. The system of claim 8, wherein: the system determines a set of gradients for each input of a set of input values; and the set of gradients is distributed to each of the one or more processors. 16. A method, comprising training a neural network by, at least in part, training different portions of a neural network separately in parallel using a plurality of processors. 17. The method of claim 16 wherein: the neural network is trained at least in part by distributing gradient information to the plurality of workers; the workers calculate different portions of a weight update in parallel; and the different portions are aggregated to produce new weight values of the neural network. 18. The method of claim 17, wherein the neural network is trained at least in part by: forwarding propagating an input through the neural network to produce an output; determining an error based at least in part on the output; and determining a gradient by at least backpropagating the error, the different portions of the weight updates based at least in part on the gradient. 19. The method of claim 18, wherein: the gradient is distributed to each of the plurality of workers; and the plurality of workers calculate the different portions of the weight update. 20. The method of claim 16, wherein each worker of the plurality of workers executes on a different processor. 21. The method of claim 16, wherein each worker of the plurality of workers executes in parallel on a graphical processing unit. 22. The method of claim 17, wherein a number of different portions of the weight update matches a number of available processors of a computer system. 23. The method of claim 17, wherein the weight update is divided into substantially equal nonoverlapping groups of node weights to produce the different portions. 24. A speech processing system comprising a neural network that takes a digital representation of sound as input and identifies elements of human speech, portions of the neural network trained to recognize human speech separately in parallel by a plurality of processes. 25. The speech processing system of claim 24 wherein the neural network: generates a plurality of weight updates in parallel; and combines the plurality of weight updates into a single weight update. 26. The speech processing system of claim 24, wherein the speech processing system further comprises one or more processors and memory to store executable instructions that, as a result of being executed by the one or more processors, cause the speech processing system to at least: obtain data representing audio from a microphone; process the data using the neural network to identify a spoken word represented in the data; and perform an action based at least in part on the identity of the spoken word. 27. The speech processing system of claim 26, wherein the action is a navigation request to be processed by a navigation system of a vehicle. |
In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1790 registers 1745. As illustrated in FIG.17F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1701-1702 and GPU memories 1720-1723. In this implementation, operations executed on GPUs 1710-1713 utilize a same virtual/effective memory address space to access processor memories 1701-1702 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of a virtual/effective address space is allocated to processor memory 1701, a second portion to second processor memory 1702, a third portion to GPU memory 1720, and so on. In at least one embodiment, an entire virtual/effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1701-1702 and GPU memories 1720-1723, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory. In one embodiment, bias/coherence management circuitry 1794A-1794E within one or more of MMUs 1739A-1739E ensures cache coherence between caches of one or more host processors (e.g., 1705) and GPUs 1710-1713 and implements biasing techniques indicating physical memories in which certain types of data should be stored. While multiple instances of bias/coherence management circuitry 1794A-1794E are illustrated in FIG.17F, bias/coherence circuitry may be implemented within an MMU of one or more host processors 1705 and/or within accelerator integration circuit 1736. One embodiment allows GPU-attached memory 1720-1723 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU-attached memory 1720-1723 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor 1705 software to setup operands and access computation results, without overhead of tradition I/O DMA data copies. Such traditional copies involve driver calls, interrupts and memory mapped I/O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU attached memory 1720-1723 without cache coherence overheads can be critical to execution time of an offloaded computation. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1710-1713. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload. In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page-granular structure (i.e., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU-attached memories 1720-1723, with or without a bias cache in GPU 1710-1713 (e.g., to cache frequently/recently used entries of a bias table). Alternatively, an entire bias table may be maintained within a GPU. In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1720-1723 is accessed prior to actual access to a GPU memory, causing the following operations. First, local requests from GPU 1710-1713 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1720-1723. Local requests from a GPU that find their page in host bias are forwarded to processor 1705 (e.g., over a high-speed link as discussed above). In one embodiment, requests from processor 1705 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU 1710-1713. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software- based mechanism, or, for a limited set of cases, a purely hardware-based mechanism. One mechanism for changing bias state employs an API call (e.g. OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, cache flushing operation is used for a transition from host processor 1705 bias to GPU bias, but is not for an opposite transition. In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1705. To access these pages, processor 1705 may request access from GPU 1710, which may or may not grant access right away. Thus, to reduce communication between processor 1705 and GPU 1710 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1705 and vice versa. Hardware structure(s) 915 are used to perform one or more embodiments. Details regarding the hardware structure(x) 915 are provided herein in conjunction with FIGS.9A and/or 9B. FIG.18 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. FIG.18 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processor(s) 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and/or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, UART controller 1830, an SPI/SDIO controller 1835, and an I.sup.2S/I.sup.2C controller 1840. In at least one embodiment, integrated circuit 1800 can include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860 including flash memory and a flash memory controller. In at least one embodiment, memory interface may be provided via a memory controller 1865 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in integrated circuit 1800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, an architecture as shown in FIGS.19A and 19B may be used to implement workers that operate in parallel to train a neural network as described above. FIGS.19A and19B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. FIGS.19A and 19B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG.19A illustrates an exemplary graphics processor 1910 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG.19B illustrates an additional exemplary graphics processor 1940 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1910 of FIG.19A is a low power graphics processor core. In at least one embodiment, graphics processor 1940 of FIG. 19B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1910, 1940 can be variants of graphics processor 1810 of FIG.18. In at least one embodiment, graphics processor 1910 includes a vertex processor 1905 and one or more fragment processor(s) 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D, through 1915N-1, and 1915N). In at least one embodiment, graphics processor 1910 can execute different shader programs via separate logic, such that vertex processor 1905 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 1915A-1915N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1905 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 1915A-1915N use primitive and vertex data generated by vertex processor 1905 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1915A-1915N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API. In at least one embodiment, graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, cache(s) 1925A-1925B, and circuit interconnect(s) 1930A-1930B. In at least one embodiment, one or more MMU(s) 1920A- 1920B provide for virtual to physical address mapping for graphics processor 1910, including for vertex processor 1905 and/or fragment processor(s) 1915A-1915N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s) 1925A-1925B. In at least one embodiment, one or more MMU(s) 1920A-1920B may be synchronized with other MMUs within system, including one or more MMUs associated with one or more application processor(s) 1805, image processors 1815, and/or video processors 1820 of FIG.18, such that each processor 1805-1820 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1930A-1930B enable graphics processor 1910 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection. In at least one embodiment, graphics processor 1940 includes one or more MMU(s) 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B of graphics processor 1910 of FIG.19A. In at least one embodiment, graphics processor 1940 includes one or more shader core(s) 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F, through 1955N-1, and 1955N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1940 includes an inter-core task manager 1945, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1955A-1955N and a tiling unit 1958 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in integrated circuit 19A and/or 19B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, graphics processor logic as shown in FIGS.20A-20B may be used to implement workers that operate in parallel to train a neural network as described above. FIGS.20A and 20B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG.20A illustrates a graphics core 2000 that may be included within graphics processor 1810 of FIG.18, in at least one embodiment, and may be a unified shader core 1955A-1955N as in FIG.19B in at least one embodiment. FIG. 20B illustrates a highly-parallel general-purpose graphics processing unit 2030 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache/shared memory 2020 that are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 can include multiple slices 2001A-2001N or partition for each core, and a graphics processor can include multiple instances of graphics core 2000. Slices 2001A-2001N can include support logic including a local instruction cache 2004A-2004N, a thread scheduler 2006A-2006N, a thread dispatcher 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N can include a set of additional function units (AFUs 2012A-2012N), floating-point units (FPU 2014A-2014N), integer arithmetic logic units (ALUs 2016-2016N), address computational units (ACU 2013A-2013N), double- precision floating-point units (DPFPU 2015A-2015N), and matrix processing units (MPU 2017A-2017N). In at least one embodiment, FPUs 2014A-2014N can perform single-precision (32- bit) and half-precision (16-bit) floating point operations, while DPFPUs 2015A-2015N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 2016A-2016N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 2017A-2017N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 2017-2017N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 2012A-2012N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics core 2000 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, graphics processor logic as shown in FIGS.20A-20B may be used to implement workers that operate in parallel to train a neural network as described above. FIG.20B illustrates a general-purpose processing unit (GPGPU) 2030 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 2030 can be linked directly to other instances of GPGPU 2030 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 2030 includes a host interface 2032 to enable a connection with a host processor. In at least one embodiment, host interface 2032 is a PCI Express interface. In at least one embodiment, host interjace 2032 can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU 2030 receives commands from a host processor and uses a global scheduler 2034 to distribute execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 can serve as a higher-level cache for cache memories within compute clusters 2036A-2036H. In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled with compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memory 2044A-2044B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, compute clusters 2036A-2036H each include a set of graphics cores, such as graphics core 2000 of FIG.20A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2036A- 2036H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 2036A-2036H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate over host interface 2032. In at least one embodiment, GPGPU 2030 includes an I/O hub 2039 that couples GPGPU 2030 with a GPU link 2040 that enables a direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment GPU link 2040 couples with a high speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device that is accessible via host interface 2032. In at least one embodiment GPU link 2040 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 2032. In at least one embodiment, GPGPU 2030 can be configured to train neural networks. In at least one embodiment, GPGPU 2030 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 2030 is used for inferencing, GPGPU may include fewer compute clusters 2036A-2036H relative to when GPGPU is used for training a neural network. In at least one embodiment, memory technology associated with memory 2044A-2044B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, inferencing configuration of GPGPU 2030 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in GPGPU 2030 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, a computing system 2100 as shown in FIG.21 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.21 is a block diagram illustrating a computing system 2100 according to at least one embodiment. In at least one embodiment, computing system 2100 includes a processing subsystem 2101 having one or more processor(s) 2102 and a system memory 2104 communicating via an interconnection path that may include a memory hub 2105. In at least one embodiment, memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processor(s) 2102. In at least one embodiment, memory hub 2105 couples with an I/O subsystem 2111 via a communication link 2106. In at least one embodiment, I/O subsystem 2111 includes an I/O hub 2107 that can enable computing system 2100 to receive input from one or more input device(s) 2108. In at least one embodiment, I/O hub 2107 can enable a display controller, which may be included in one or more processor(s) 2102, to provide outputs to one or more display device(s) 2110A. In at least one embodiment, one or more display device(s) 2110A coupled with I/O hub 2107 can include a local, internal, or embedded display device. In at least one embodiment, processing subsystem 2101 includes one or more parallel processor(s) 2112 coupled to memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, communication link 2113 may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 2112 form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processor(s) 2112 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 2110A coupled via I/O Hub 2107. In at least one embodiment, one or more parallel processor(s) 2112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 2110B. In at least one embodiment, a system storage unit 2114 can connect to I/O hub 2107 to provide a storage mechanism for computing system 2100. In at least one embodiment, an I/O switch 2116 can be used to provide an interface mechanism to enable connections between I/O hub 2107 and other components, such as a network adapter 2118 and/or wireless network adapter 2119 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 2120. In at least one embodiment, network adapter 2118 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios. In at least one embodiment, computing system 2100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I/O hub 2107. In at least one embodiment, communication paths interconnecting various components in FIG.21 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and/or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols. In at least one embodiment, one or more parallel processor(s) 2112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, one or more parallel processor(s) 2112 incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 2112, memory hub 2105, processor(s) 2102, and I/O hub 2107 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2100 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 2100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi- chip modules into a modular computing system. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in system FIG.2100 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, a parallel processor as shown in FIG.22A may be used to implement workers that operate in parallel to train a neural network as described above. PROCESSORS FIG.22A illustrates a parallel processor 2200 according to at least on embodiment. In at least one embodiment, various components of parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 2200 is a variant of one or more parallel processor(s) 2112 shown in FIG.21 according to an exemplary embodiment. In at least one embodiment, parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, parallel processing unit 2202 includes an I/O unit 2204 that enables communication with other devices, including other instances of parallel processing unit 2202. In at least one embodiment, I/O unit 2204 may be directly connected to other devices. In at least one embodiment, I/O unit 2204 connects with other devices via use of a hub or switch interface, such as memory hub 2105. In at least one embodiment, connections between memory hub 2105 and I/O unit 2204 form a communication link 2113. In at least one embodiment, I/O unit 2204 connects with a host interface 2206 and a memory crossbar 2216, where host interface 2206 receives commands directed to performing processing operations and memory crossbar 2216 receives commands directed to performing memory operations. In at least one embodiment, when host interface 2206 receives a command buffer via I/O unit 2204, host interface 2206 can direct work operations to perform those commands to a front end 2208. In at least one embodiment, front end 2208 couples with a scheduler 2210, which is configured to distribute commands or other work items to a processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is properly configured and in a valid state before tasks are distributed to processing cluster array 2212 of processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler 2210 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can prove workloads for scheduling on processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array 2212 by scheduler 2210 logic within a microcontroller including scheduler 2210. In at least one embodiment, processing cluster array 2212 can include up to “N” processing clusters (e.g., cluster 2214A, cluster 2214B, through cluster 2214N). In at least one embodiment, each cluster 2214A-2214N of processing cluster array 2212 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2210 can allocate work to clusters 2214A-2214N of processing cluster array 2212 using various scheduling and/or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 2210, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of processing cluster array 2212 can be allocated for processing different types of programs or for performing different types of computations. In at least one embodiment, processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2212 can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations. In at least one embodiment, processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2212 can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2212 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2202 can transfer data from system memory via I/O unit 2204 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 2222) during processing, then written back to system memory. In at least one embodiment, when parallel processing unit 2202 is used to perform graphics processing, scheduler 2210 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 2214A-2214N of processing cluster array 2212. In at least one embodiment, portions of processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 2214A-2214N may be stored in buffers to allow intermediate data to be transmitted between clusters 2214A-2214N for further processing. In at least one embodiment, processing cluster array 2212 can receive processing tasks to be executed via scheduler 2210, which receives commands defining processing tasks from front end 2208. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 2210 may be configured to fetch indices corresponding to tasks or may receive indices from front end 2208. In at least one embodiment, front end 2208 can be configured to ensure processing cluster array 2212 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated. In at least one embodiment, each of one or more instances of parallel processing unit 2202 can couple with parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar 2216, which can receive memory requests from processing cluster array 2212 as well as I/O unit 2204. In at least one embodiment, memory crossbar 2216 can access parallel processor memory 2222 via a memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B, through partition unit 2220N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 2222. In at least one embodiment, a number of partition units 2220A-2220N is configured to be equal to a number of memory units, such that a first partition unit 2220A has a corresponding first memory unit 2224A, a second partition unit 2220B has a corresponding memory unit 2224B, and an Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, a number of partition units 2220A-2220N may not be equal to a number of memory devices. In at least one embodiment, memory units 2224A-2224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 2224A-2224N, allowing partition units 2220A-2220N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 2222. In at least one embodiment, a local instance of parallel processor memory 2222 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. In at least one embodiment, any one of clusters 2214A-2214N of processing cluster array 2212 can process data that will be written to any of memory units 2224A-2224N within parallel processor memory 2222. In at least one embodiment, memory crossbar 2216 can be configured to transfer an output of each cluster 2214A-2214N to any partition unit 2220A- 2220N or to another cluster 2214A-2214N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2214A-2214N can communicate with memory interface 2218 through memory crossbar 2216 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2216 has a connection to memory interface 2218 to communicate with I/O unit 2204, as well as a connection to a local instance of parallel processor memory 2222, enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to parallel processing unit 2202. In at least one embodiment, memory crossbar 2216 can use virtual channels to separate traffic streams between clusters 2214A-2214N and partition units 2220A-2220N. In at least one embodiment, multiple instances of parallel processing unit 2202 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2202 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2202 or parallel processor 2200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. FIG.22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, partition unit 2220 is an instance of one of partition units 2220A-2220N of FIG.22A. In at least one embodiment, partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a ROP 2226 (raster operations unit). L2 cache 2221 is a read/write cache that is configured to perform load and store operations received from memory crossbar 2216 and ROP 2226. In at least one embodiment, read misses and urgent write-back requests are output by L2 cache 2221 to frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 2225 for processing. In at least one embodiment, frame buffer interface 2225 interfaces with one of memory units in parallel processor memory, such as memory units 2224A-2224N of FIG.22 (e.g., within parallel processor memory 2222). In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stencil, z test, blending, and like. In at least one embodiment, ROP 2226 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. Type of compression that is performed by ROP 2226 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per- tile basis. In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., cluster 2214A-2214N of FIG.22) instead of within partition unit 2220. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 2216 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s) 2110 of FIG.21, routed for further processing by processor(s) 2102, or routed for further processing by one of processing entities within parallel processor 2200 of FIG.22A. FIG.22C is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 2214A-2214N of FIG.22. In at least one embodiment, processing cluster 2214 can be configured to execute many threads in parallel, where term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters. In at least one embodiment, operation of processing cluster 2214 can be controlled via a pipeline manager 2232 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2232 receives instructions from scheduler 2210 of FIG.22 and manages execution of those instructions via a graphics multiprocessor 2234 and/or a texture unit 2236. In at least one embodiment, graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 2214. In at least one embodiment, one or more instances of graphics multiprocessor 2234 can be included within a processing cluster 2214. In at least one embodiment, graphics multiprocessor 2234 can process data and a data crossbar 2240 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 2232 can facilitate distribution of processed data by specifying destinations for processed data to be distributed vis data crossbar 2240. In at least one embodiment, each graphics multiprocessor 2234 within processing cluster 2214 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present. In at least one embodiment, instructions transmitted to processing cluster 2214 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 2234. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2234. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2234. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 2234, processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 2234. In at least one embodiment, graphics multiprocessor 2234 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2234 can forego an internal cache and use a cache memory (e.g., L1 cache 2248) within processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 also has access to L2 caches within partition units (e.g., partition units 2220A-2220N of FIG.22) that are shared among all processing clusters 2214 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2234 may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit 2202 may be used as global memory. In at least one embodiment, processing cluster 2214 includes multiple instances of graphics multiprocessor 2234 can share common instructions and data, which may be stored in L1 cache 2248. In at least one embodiment, each processing cluster 2214 may include an MMU 2245 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 2245 may reside within memory interface 2218 of FIG.22. In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile (talk more about tiling) and optionally a cache line index. In at least one embodiment, MMU 2245 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 2234 or L1 cache or processing cluster 2214. In at least one embodiment, physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, cache line index may be used to determine whether a request for a cache line is a hit or miss. In at least one embodiment, a processing cluster 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2234 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2234 outputs processed tasks to data crossbar 2240 to provide processed task to another processing cluster 2214 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2216. In at least one embodiment, preROP 2242 (pre- raster operations unit) is configured to receive data from graphics multiprocessor 2234, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 2220A-2220N of FIG.22). In at least one embodiment, PreROP 2242 unit can perform optimizations for color blending, organize pixel color data, and perform address translations. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics processing cluster 2214 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, a graphics multiprocessor as shown in FIG.22D may be used to implement workers that operate in parallel to train a neural network as described above. FIG.22D shows a graphics multiprocessor 2234 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 2234 couples with pipeline manager 2232 of processing cluster 2214. In at least one embodiment, graphics multiprocessor 2234 has an execution pipeline including but not limited to an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general purpose graphics processing unit (GPGPU) cores 2262, and one or more load/store units 2266. GPGPU cores 2262 and load/store units 2266 are coupled with cache memory 2272 and shared memory 2270 via a memory and cache interconnect 2268. In at least one embodiment, instruction cache 2252 receives a stream of instructions to execute from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched for execution by instruction unit 2254. In at least one embodiment, instruction unit 2254 can dispatch instructions as thread groups (e.g., warps), with each thread of thread group assigned to a different execution unit within GPGPU core 2262. In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load/store units 2266. In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 2262, load/store units 2266) of graphics multiprocessor 2234. In at least one embodiment, register file 2258 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 2258. In at least one embodiment, register file 2258 is divided between different warps being executed by graphics multiprocessor 2234. In at least one embodiment, GPGPU cores 2262 can each include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 2234. GPGPU cores 2262 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 2262 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754- 2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2234 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores can also include fixed or special function logic. In at least one embodiment, GPGPU cores 2262 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit. In at least one embodiment, memory and cache interconnect 2268 is an interconnect network that connects each functional unit of graphics multiprocessor 2234 to register file 2258 and to shared memory 2270. In at least one embodiment, memory and cache interconnect 2268 is a crossbar interconnect that allows load/store unit 2266 to implement load and store operations between shared memory 2270 and register file 2258. In at least one embodiment, register file 2258 can operate at a same frequency as GPGPU cores 2262, thus data transfer between GPGPU cores 2262 and register file 2258 is very low latency. In at least one embodiment, shared memory 2270 can be used to enable communication between threads that execute on functional units within graphics multiprocessor 2234. In at least one embodiment, cache memory 2272 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 2236. In at least one embodiment, shared memory 2270 can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores 2262 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 2272. In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, GPU may be integrated on same package or chip as cores and communicatively coupled to cores over an internal processor bus/interconnect (i.e., internal to package or chip). In at least one embodiment, regardless of manner in which GPU is connected, processor cores may allocate work to GPU in form of sequences of commands/instructions contained in a work descriptor. In at least one embodiment, GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics multiprocessor 2234 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, multi-GPU computing system as shown in FIG.23 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.23 illustrates a multi-GPU computing system 2300, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 2300 can include a processor 2302 coupled to multiple general purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, host interface switch 2304 is a PCI express switch device that couples processor 2302 to a PCI express bus over which processor 2302 can communicate with GPGPUs 2306A-D. GPGPUs 2306A-D can interconnect via a set of high-speed point to point GPU to GPU links 2316. In at least one embodiment, GPU to GPU links 2316 connect to each of GPGPUs 2306A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2316 enable direct communication between each of GPGPUs 2306A-D without requiring communication over host interface bus 2304 to which processor 2302 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 2316, host interface bus 2304 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2300, for example, via one or more network devices. While in at least one embodiment GPGPUs 2306A-D connect to processor 2302 via host interface switch 2304, in at least one embodiment processor 2302 includes direct support for P2P GPU links 2316 and can connect directly to GPGPUs 2306A-D. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in multi-GPU computing system 2300 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, graphics processor as shown in FIG.24 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.24 is a block diagram of a graphics processor 2400, according to at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front-end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 2400 receives batches of commands via ring interconnect 2402. In at least one embodiment, incoming commands are interpreted by a command streamer 2403 in pipeline front-end 2404. In at least one embodiment, graphics processor 2400 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, command streamer 2403 supplies commands to geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, command streamer 2403 supplies commands to a video front end 2434, which couples with a media engine 2437. In at least one embodiment, media engine 2437 includes a Video Quality Engine (VQE) 2430 for video and image post-processing and a multi-format encode/decode (MFX) 2433 engine to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline 2436 and media engine 2437 each generate execution threads for thread execution resources provided by at least one graphics core 2480A. In at least one embodiment, graphics processor 2400 includes scalable thread execution resources featuring modular cores 2480A-2480N (sometimes referred to as core slices), each having multiple sub-cores 2450A-550N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2400 can have any number of graphics cores 2480A through 2480N. In at least one embodiment, graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, graphics processor 2400 is a low power processor with a single sub-core (e.g., 2450A). In at least one embodiment, graphics processor 2400 includes multiple graphics cores 2480A-2480N, each including a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each sub-core in first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media/texture samplers 2454A-2454N. In at least one embodiment, each sub-core in second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each sub-core 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, inference and/or training logic 915 may be used in graphics processor 2400 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. In at least one embodiment, a micro-architecture as shown in FIG.25 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.25 is a block diagram illustrating micro-architecture for a processor 2500 that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor 2500 may perform instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor 2510 may include registers to store packed data, such as 64-bit wide MMX TM registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors 2510 may perform instructions to accelerate machine learning or deep learning algorithms, training, or inferencing. In at least one embodiment, processor 2500 includes an in-order front end (“front end”) 2501 to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, an instruction prefetcher 2526 fetches instructions from memory and feeds instructions to an instruction decoder 2528 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 2528 decodes a received instruction into one or more operations called “micro-instructions” or “micro- operations” (also called “micro ops” or “uops”) that machine may execute. In at least one embodiment, instruction decoder 2528 parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache 2530 may assemble decoded uops into program ordered sequences or traces in a uop queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, a microcode ROM 2532 provides uops needed to complete operation. In at least one embodiment, some instructions may be converted into a single micro- op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder 2528 may access microcode ROM 2532 to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder 2528. In at least one embodiment, an instruction may be stored within microcode ROM 2532 should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache 2530 refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2532 in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 2532 finishes sequencing micro-ops for an instruction, front end 2501 of machine may resume fetching micro-ops from trace cache 2530. In at least one embodiment, out-of-order execution engine (“out of order engine”) 2503 may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down pipeline and get scheduled for execution. out-of- order execution engine 2503 includes, without limitation, an allocator/register renamer 2540, a memory uop queue 2542, an integer/floating point uop queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow/general floating point scheduler (“slow/general FP scheduler”) 2504, and a simple floating point scheduler (“simple FP scheduler”) 2506. In at least one embodiment, fast schedule 2502, slow/general floating point scheduler 2504, and simple floating point scheduler 2506 are also collectively referred to herein as “uop schedulers 2502, 2504, 2506.” Allocator/register renamer 2540 allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer 2540 renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer 2540 also allocates an entry for each uop in one of two uop queues, memory uop queue 2542 for memory operations and integer/floating point uop queue 2544 for non-memory operations, in front of memory scheduler 2546 and uop schedulers 2502, 2504, 2506. In at least one embodiment, uop schedulers 2502, 2504, 2506, determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler 2502 of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler 2504 and simple floating point scheduler 2506 may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers 2502, 2504, 2506 arbitrate for dispatch ports to schedule uops for execution. In at least one embodiment, execution block b11 includes, without limitation, an integer register file/bypass network 2508, a floating point register file/bypass network (“FP register file/bypass network”) 2510, address generation units (“AGUs”) 2512 and 2514, fast Arithmetic Logic Units (ALUs) (“fast ALUs”) 2516 and 2518, a slow Arithmetic Logic Unit (“slow ALU”) 2520, a floating point ALU (“FP”) 2522, and a floating point move unit (“FP move”) 2524. In at least one embodiment, integer register file/bypass network 2508 and floating point register file/bypass network 2510 are also referred to herein as “register files 2508, 2510.” In at least one embodiment, AGUSs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating point ALU 2522, and floating point move unit 2524 are also referred to herein as “execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524.” In at least one embodiment, execution block b11 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination. In at least one embodiment, register files 2508, 2510 may be arranged between uop schedulers 2502, 2504, 2506, and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file/bypass network 2508 performs integer operations. In at least one embodiment, floating point register file/bypass network 2510 performs floating point operations. In at least one embodiment, each of register files 2508, 2510 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files 2508, 2510 may communicate data with each other. In at least one embodiment, integer register file/bypass network 2508 may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network 2510 may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width. In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524 may execute instructions. In at least one embodiment, register files 2508, 2510 store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor 2500 may include, without limitation, any number and combination of execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524. In at least one embodiment, floating point ALU 2522 and floating point move unit 2524, may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 2522 may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs 2516, 2518. In at least one embodiment, fast ALUS 2516, 2518 may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2520 as slow ALU 2520 may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUS 2512, 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 2522 and floating point move unit 2524 may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU 2522 and floating point move unit 2524 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. In at least one embodiment, uop schedulers 2502, 2504, 2506, dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor 2500, processor 2500 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in data cache, there may be dependent operations in flight in pipeline that have left scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations. In at least one embodiment, term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of processor (from a programmer’s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment portions or all of inference and/or training logic 915 may be incorporated into EXE Block 2511 and other memory or registers shown or not shown. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs illustrated in EXE Block 2511. Moreover, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of EXE Block 2511 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.26 illustrates a deep learning application processor 2600, according to at least one embodiment. In at least one embodiment, deep learning application processor 2600 uses instructions that, if executed by deep learning application processor 2600, cause deep learning application processor 2600 to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2600 is an application-specific integrated circuit (ASIC). In at least one embodiment, application processor 2600 performs matrix multiply operations either “hard- wired” into hardware as a result of performing one or more instructions or both. In at least one embodiment, deep learning application processor 2600 includes, without limitation, processing clusters 2610(1)-2610(12), Inter-Chip Links (“ICLs”) 2620(1)-2620(12), Inter- Chip Controllers (“ICCs”) 2630(1)-2630(2), high bandwidth memory second generation (“HBM2”) 2640(1)-2640(4), memory controllers (“Mem Ctrlrs”) 2642(1)-2642(4), high bandwidth memory physical layer (“HBM PHY”) 2644(1)-2644(4), a management-controller central processing unit (“management-controller CPU”) 2650, a Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input/Output block (“SPI, I2C, GPIO”) 2660, a peripheral component interconnect express controller and direct memory access block (“PCIe Controller and DMA”) 2670, and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2680. In at least one embodiment, processing clusters 2610 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 may include, without limitation, any number and type of processors. In at least one embodiment, deep learning application processor 2600 may include any number and type of processing clusters 2600. In at least one embodiment, Inter-Chip Links 2620 are bi-directional. In at least one embodiment, Inter-Chip Links 2620 and Inter-Chip Controllers 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information resulting from performing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2600 may include any number (including zero) and type of ICLs 2620 and ICCs 2630. In at least one embodiment, HBM2s 2640 provide a total of 32 Gigabytes (GB) of memory. HBM22640(i) is associated with both memory controller 2642(i) and HBM PHY 2644(i). In at least one embodiment, any number of HBM2s 2640 may provide any type and total amount of high bandwidth memory and may be associated with any number (including zero) and type of memory controllers 2642 and HBM PHYs 2644. In at least one embodiment, SPI, I2C, GPIO 2660, PCIe Controller and DMA 2670, and/or PCIe 2680 may be replaced with any number and type of blocks that enable any number and type of communication standards in any technically feasible fashion. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to deep learning application processor 2600. In at least one embodiment, deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep learning application processor 2600. In at least one embodiment, processor 2600 may be used to perform one or more neural network use cases described herein. In at least one embodiment, a neuromorphic processor as shown in FIG.27 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.27 is a block diagram of a neuromorphic processor 2700, according to at least one embodiment. In at least one embodiment, neuromorphic processor 2700 may receive one or more inputs from sources external to neuromorphic processor 2700. In at least one embodiment, these inputs may be transmitted to one or more neurons 2702 within neuromorphic processor 2700. In at least one embodiment, neurons 2702 and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2700 may include, without limitation, thousands or millions of instances of neurons 2702, but any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, neurons 2702 may generate outputs that may be transmitted to inputs of other instances of neurons 2702. For example, in at least one embodiment, neuron inputs 2704 and neuron outputs 2706 may be interconnected via synapses 2708. In at least one embodiment, neurons 2702 and synapses 2708 may be interconnected such that neuromorphic processor 2700 operates to process or analyze information received by neuromorphic processor 2700. In at least one embodiment, neurons 2702 may transmit an output pulse (or “fire” or “spike”) when inputs received through neuron input 2704 exceed a threshold. In at least one embodiment, neurons 2702 may sum or integrate signals received at neuron inputs 2704. For example, in at least one embodiment, neurons 2702 may be implemented as leaky integrate-and-fire neurons, wherein if a sum (referred to as a “membrane potential”) exceeds a threshold value, neuron 2702 may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs 2704 into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron inputs 2704 rapidly enough to exceed a threshold value (i.e., before a membrane potential decays too low to fire). In at least one embodiment, neurons 2702 may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neurons 2702 may include, without limitation, comparator circuits or logic that generate an output spike at neuron output 2706 when result of applying a transfer function to neuron input 2704 exceeds a threshold. In at least one embodiment, once neuron 2702 fires, it may disregard previously received input information by, for example, resetting a membrane potential to 0 or another suitable default value. In at least one embodiment, once membrane potential is reset to 0, neuron 2702 may resume normal operation after a suitable period of time (or refractory period). In at least one embodiment, neurons 2702 may be interconnected through synapses 2708. In at least one embodiment, synapses 2708 may operate to transmit signals from an output of a first neuron 2702 to an input of a second neuron 2702. In at least one embodiment, neurons 2702 may transmit information over more than one instance of synapse 2708. In at least one embodiment, one or more instances of neuron output 2706 may be connected, via an instance of synapse 2708, to an instance of neuron input 2704 in same neuron 2702. In at least one embodiment, an instance of neuron 2702 generating an output to be transmitted over an instance of synapse 2708 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2708. In at least one embodiment, an instance of neuron 2702 receiving an input transmitted over an instance of synapse 2708 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2708. Because an instance of neuron 2702 may receive inputs from one or more instances of synapse 2708, and may also transmit outputs over one or more instances of synapse 2708, a single instance of neuron 2702 may therefore be both a “pre-synaptic neuron” and “post- synaptic neuron,” with respect to various instances of synapses 2708, in at least one embodiment. In at least one embodiment, neurons 2702 may be organized into one or more layers. Each instance of neuron 2702 may have one neuron output 2706 that may fan out through one or more synapses 2708 to one or more neuron inputs 2704. In at least one embodiment, neuron outputs 2706 of neurons 2702 in a first layer 2710 may be connected to neuron inputs 2704 of neurons 2702 in a second layer 2712. In at least one embodiment, layer 2710 may be referred to as a “feed-forward layer.” In at least one embodiment, each instance of neuron 2702 in an instance of first layer 2710 may fan out to each instance of neuron 2702 in second layer 2712. In at least one embodiment, first layer 2710 may be referred to as a “fully connected feed-forward layer.” In at least one embodiment, each instance of neuron 2702 in an instance of second layer 2712 may fan out to fewer than all instances of neuron 2702 in a third layer 2714. In at least one embodiment, second layer 2712 may be referred to as a “sparsely connected feed-forward layer.” In at least one embodiment, neurons 2702 in second layer 2712 may fan out to neurons 2702 in multiple other layers, including to neurons 2702 in (same) second layer 2712. In at least one embodiment, second layer 2712 may be referred to as a “recurrent layer.” Neuromorphic processor 2700 may include, without limitation, any suitable combination of recurrent layers and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers. In at least one embodiment, neuromorphic processor 2700 may include, without limitation, a reconfigurable interconnect architecture or dedicated hard wired interconnects to connect synapse 2708 to neurons 2702. In at least one embodiment, neuromorphic processor 2700 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2702 as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses 2708 may be connected to neurons 2702 using an interconnect fabric, such as network-on-chip, or with dedicated connections. In at least one embodiment, synapse interconnections and components thereof may be implemented using circuitry or logic. FIG.28 is a block diagram of a processing system, according to at least one embodiment. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, system 2800 can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2800 is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system 2800 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2800 is a television or set top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808. In at least one embodiment, one or more processors 2802 each include one or more processor cores 2807 to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2807 is configured to process a specific instruction set 2809. In at least one embodiment, instruction set 2809 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, processor cores 2807 may each process a different instruction set 2809, which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2807 may also include other processing devices, such a Digital Signal Processor (DSP). In at least one embodiment, processor 2802 includes cache memory 2804. In at least one embodiment, processor 2802 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores 2807 using known cache coherency techniques. In at least one embodiment, register file 2806 is additionally included in processor 2802 which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file 2806 may include general-purpose registers or other registers. In at least one embodiment, one or more processor(s) 2802 are coupled with one or more interface bus(es) 2810 to transmit communication signals such as address, data, or control signals between processor 2802 and other components in system 2800. In at least one embodiment interface bus 2810, in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface 2810 is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In at least one embodiment processor(s) 2802 include an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, memory controller 2816 facilitates communication between a memory device and other components of system 2800, while platform controller hub (PCH) 2830 provides connections to I/O devices via a local I/O bus. In at least one embodiment, memory device 2820 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In at least one embodiment memory device 2820 can operate as system memory for system 2800, to store data 2822 and instructions 2821 for use when one or more processors 2802 executes an application or process. In at least one embodiment, memory controller 2816 also couples with an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 in processors 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 can connect to processor(s) 2802. In at least one embodiment display device 2811 can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 2811 can include a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications. In at least one embodiment, platform controller hub 2830 enables peripherals to connect to memory device 2820 and processor 2802 via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, touch sensors 2825, a data storage device 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2824 can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensors 2825 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2826 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 2834 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high definition audio controller. In at least one embodiment, system 2800 includes an optional legacy I/O controller 2840 for coupling legacy (e.g., Personal System 2 (PS/2)) devices to system. In at least one embodiment, platform controller hub 2830 can also connect to one or more Universal Serial Bus (USB) controllers 2842 connect input devices, such as keyboard and mouse 2843 combinations, a camera 2844, or other USB input devices. In at least one embodiment, an instance of memory controller 2816 and platform controller hub 2830 may be integrated into a discreet external graphics processor, such as external graphics processor 2812. In at least one embodiment, platform controller hub 2830 and/or memory controller 2816 may be external to one or more processor(s) 2802. For example, in at least one embodiment, system 2800 can include an external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s) 2802. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment portions or all of inference and/or training logic 915 may be incorporated into graphics processor 2800. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline 2812. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor 2800 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.29 is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908, according to at least one embodiment. In at least one embodiment, processor 2900 can include additional cores up to and including additional core 2902N represented by dashed lined boxes. In at least one embodiment, each of processor cores 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core also has access to one or more shared cached units 2906. In at least one embodiment, internal cache units 2904A-2904N and shared cache units 2906 represent a cache memory hierarchy within processor 2900. In at least one embodiment, cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units 2906 and 2904A- 2904N. In at least one embodiment, processor 2900 may also include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCI express busses. In at least one embodiment, system agent core 2910 provides management functionality for various processor components. In at least one embodiment, system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown). In at least one embodiment, one or more of processor cores 2902A-2902N include support for simultaneous multi-threading. In at least one embodiment, system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multi- threaded processing. In at least one embodiment, system agent core 2910 may additionally include a power control unit (PCU), which includes logic and components to regulate one or more power states of processor cores 2902A-2902N and graphics processor 2908. In at least one embodiment, processor 2900 additionally includes graphics processor 2908 to execute graphics processing operations. In at least one embodiment, graphics processor 2908 couples with shared cache units 2906, and system agent core 2910, including one or more integrated memory controllers 2914. In at least one embodiment, system agent core 2910 also includes a display controller 2911 to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2911 may also be a separate module coupled with graphics processor 2908 via at least one interconnect, or may be integrated within graphics processor 2908. In at least one embodiment, a ring based interconnect unit 2912 is used to couple internal components of processor 2900. In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor 2908 couples with ring interconnect 2912 via an I/O link 2913. In at least one embodiment, I/O link 2913 represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module 2918, such as an eDRAM module. In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 use embedded memory modules 2918 as a shared Last Level Cache. In at least one embodiment, processor cores 2902A-2902N are homogenous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 2902A-2902N execute a common instruction set, while one or more other cores of processor cores 2902A-29-02N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In at least one embodiment, processor 2900 can be implemented on one or more chips or as an SoC integrated circuit. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment portions or all of inference and/or training logic 915 may be incorporated into graphics processor 2910. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline 2812, graphics core(s) 2915A, shared function logic 2916, graphics core(s) 2915B, shared function logic 2920, or other logic in FIG.29. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor 2910 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.30 is a block diagram of a graphics processor 3000, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In at least one embodiment, graphics processor 3000 communicates via a memory mapped I/O interface to registers on graphics processor 3000 and with commands placed into memory. In at least one embodiment, graphics processor 3000 includes a memory interface 3014 to access memory. In at least one embodiment, memory interface 3014 is an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory. In at least one embodiment, graphics processor 3000 also includes a display controller 3002 to drive display output data to a display device 3020. In at least one embodiment, display controller 3002 includes hardware for one or more overlay planes for display device 3020 and composition of multiple layers of video or user interface elements. In at least one embodiment, display device 3020 can be an internal or external display device. In at least one embodiment, display device 3020 is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, graphics processor 3000 includes a video codec engine 3006 to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG- 2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats. In at least one embodiment, graphics processor 3000 includes a block image transfer (BLIT) engine 3004 to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE) 3010. In at least one embodiment, GPE 3010 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations. In at least one embodiment, GPE 3010 includes a 3D pipeline 3012 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.).3D pipeline 3012 includes programmable and fixed function elements that perform various tasks and/or spawn execution threads to a 3D/Media sub-system 3015. While 3D pipeline 3012 can be used to perform media operations, in at least one embodiment, GPE 3010 also includes a media pipeline 3016 that is used to perform media operations, such as video post-processing and image enhancement. In at least one embodiment, media pipeline 3016 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine 3006. In at least one embodiment, media pipeline 3016 additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system 3015. In at least one embodiment, spawned threads perform computations for media operations on one or more graphics execution units included in 3D/Media sub-system 3015. In at least one embodiment, 3D/Media subsystem 3015 includes logic for executing threads spawned by 3D pipeline 3012 and media pipeline 3016. In at least one embodiment, 3D pipeline 3012 and media pipeline 3016 send thread execution requests to 3D/Media subsystem 3015, which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. In at least one embodiment, execution resources include an array of graphics execution units to process 3D and media threads. In at least one embodiment, 3D/Media subsystem 3015 includes one or more internal caches for thread instructions and data. In at least one embodiment, subsystem 3015 also includes shared memory, including registers and addressable memory, to share data between threads and to store output data. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment portions or all of inference and/or training logic 915 may be incorporated into graphics processor 3000. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline 3012. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor 3000 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.31 is a block diagram of a graphics processing engine 3110 of a graphics processor in accordance with at least one embodiment. In at least one embodiment, graphics processing engine (GPE) 3110 is a version of GPE 3010 shown in FIG.30. In at least one embodiment, media pipeline 3016 is optional and may not be explicitly included within GPE 3110. In at least one embodiment, a separate media and/or image processor is coupled to GPE 3110. In at least one embodiment, GPE 3110 is coupled to or includes a command streamer 3103, which provides a command stream to 3D pipeline 3012 and/or media pipelines 3016. In at least one embodiment, command streamer 3103 is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command streamer 3103 receives commands from memory and sends commands to 3D pipeline 3012 and/or media pipeline 3016. In at least one embodiment, commands are instructions, primitives, or micro-operations fetched from a ring buffer, which stores commands for 3D pipeline 3012 and media pipeline 3016. In at least one embodiment, a ring buffer can additionally include batch command buffers storing batches of multiple commands. In at least one embodiment, commands for 3D pipeline 3012 can also include references to data stored in memory, such as but not limited to vertex and geometry data for 3D pipeline 3012 and/or image data and memory objects for media pipeline 3016. In at least one embodiment, 3D pipeline 3012 and media pipeline 3016 process commands and data by performing operations or by dispatching one or more execution threads to a graphics core array 3114. In at least one embodiment, graphics core array 3114 includes one or more blocks of graphics cores (e.g., graphics core(s) 3115A, graphics core(s) 3115B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic, including inference and/or training logic 915 in FIG.9A and FIG.9B. In at least one embodiment, 3D pipeline 3012 includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 3114. In at least one embodiment, graphics core array 3114 provides a unified block of execution resources for use in processing shader programs. In at least one embodiment, multi-purpose execution logic (e.g., execution units) within graphics core(s) 3115A-3115B of graphic core array 3114 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders. In at least one embodiment, graphics core array 3114 also includes execution logic to perform media functions, such as video and/or image processing. In at least one embodiment, execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. In at least one embodiment, output data generated by threads executing on graphics core array 3114 can output data to memory in a unified return buffer (URB) 3118. URB 3118 can store data for multiple threads. In at least one embodiment, URB 3118 may be used to send data between different threads executing on graphics core array 3114. In at least one embodiment, URB 3118 may additionally be used for synchronization between threads on graphics core array 3114 and fixed function logic within shared function logic 3120. In at least one embodiment, graphics core array 3114 is scalable, such that graphics core array 3114 includes a variable number of graphics cores, each having a variable number of execution units based on a target power and performance level of GPE 3110. In at least one embodiment, execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed. In at least one embodiment, graphics core array 3114 is coupled to shared function logic 3120 that includes multiple resources that are shared between graphics cores in graphics core array 3114. In at least one embodiment, shared functions performed by shared function logic 3120 are embodied in hardware logic units that provide specialized supplemental functionality to graphics core array 3114. In at least one embodiment, shared function logic 3120 includes but is not limited to sampler 3121, math 3122, and inter-thread communication (ITC) 3123 logic. In at least one embodiment, one or more cache(s) 3125 are included in or couple to shared function logic 3120. In at least one embodiment, a shared function is used if demand for a specialized function is insufficient for inclusion within graphics core array 3114. In at least one embodiment, a single instantiation of a specialized function is used in shared function logic 3120 and shared among other execution resources within graphics core array 3114. In at least one embodiment, specific shared functions within shared function logic 3120 that are used extensively by graphics core array 3114 may be included within shared function logic 3116 within graphics core array 3114. In at least one embodiment, shared function logic 3116 within graphics core array 3114 can include some or all logic within shared function logic 3120. In at least one embodiment, all logic elements within shared function logic 3120 may be duplicated within shared function logic 3116 of graphics core array 3114. In at least one embodiment, shared function logic 3120 is excluded in favor of shared function logic 3116 within graphics core array 3114. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment portions or all of inference and/or training logic 915 may be incorporated into graphics processor 3110. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline 3012, graphics core(s) 3115A, shared function logic 3116, graphics core(s) 3115B, shared function logic 3120, or other logic in FIG.31. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor 3110 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.32 is a block diagram of hardware logic of a graphics processor core 3200, according to at least one embodiment described herein. In at least one embodiment, graphics processor core 3200 is included within a graphics core array. In at least one embodiment, graphics processor core 3200, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 3200 is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3200 can include a fixed function block 3230 coupled with multiple sub-cores 3201A-3201F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic. In at least one embodiment, fixed function block 3230 includes a geometry/fixed function pipeline 3236 that can be shared by all sub-cores in graphics processor 3200, for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline 3236 includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers. In at least one embodiment fixed function block 3230 also includes a graphics SoC interface 3237, a graphics microcontroller 3238, and a media pipeline 3239. Graphics SoC interface 3237 provides an interface between graphics core 3200 and other processor cores within a system on a chip integrated circuit. In at least one embodiment, graphics microcontroller 3238 is a programmable sub-processor that is configurable to manage various functions of graphics processor 3200, including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline 3239 includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 3239 implement media operations via requests to compute or sampling logic within sub-cores 3201-3201F. In at least one embodiment, SoC interface 3237 enables graphics core 3200 to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 3237 can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core 3200 and CPUs within an SoC. In at least one embodiment, SoC interface 3237 can also implement power management controls for graphics core 3200 and enable an interface between a clock domain of graphic core 3200 and other clock domains within an SoC. In at least one embodiment, SoC interface 3237 enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline 3239, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 3236, geometry and fixed function pipeline 3214) when graphics processing operations are to be performed. In at least one embodiment, graphics microcontroller 3238 can be configured to perform various scheduling and management tasks for graphics core 3200. In at least one embodiment, graphics microcontroller 3238 can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays 3202A- 3202F, 3204A-3204F within sub-cores 3201A-3201F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core 3200 can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre- empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller 3238 can also facilitate low-power or idle states for graphics core 3200, providing graphics core 3200 with an ability to save and restore registers within graphics core 3200 across low-power state transitions independently from an operating system and/or graphics driver software on a system. In at least one embodiment, graphics core 3200 may have greater than or fewer than illustrated sub-cores 3201A-3201F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 3200 can also include shared function logic 3210, shared and/or cache memory 3212, a geometry/fixed function pipeline 3214, as well as additional fixed function logic 3216 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 3210 can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core 3200. Shared and/or cache memory 3212 can be a last-level cache for N sub-cores 3201A-3201F within graphics core 3200 and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline 3214 can be included instead of geometry/fixed function pipeline 3236 within fixed function block 3230 and can include same or similar logic units. In at least one embodiment, graphics core 3200 includes additional fixed function logic 3216 that can include various fixed function acceleration logic for use by graphics core 3200. In at least one embodiment, additional fixed function logic 3216 includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline 3216, 3236, and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic 3216. In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic 3216 can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase. In at least one embodiment, additional fixed function logic 3216 can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing. In at least one embodiment, within each graphics sub-core 3201A-3201F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores 3201A-3201F include multiple EU arrays 3202A-3202F, 3204A-3204F, thread dispatch and inter-thread communication (TD/IC) logic 3203A-3203F, a 3D (e.g., texture) sampler 3205A-3205F, a media sampler 3206A-3206F, a shader processor 3207A-3207F, and shared local memory (SLM) 3208A-3208F. EU arrays 3202A-3202F, 3204A-3204F each include multiple execution units, which are general- purpose graphics processing units capable of performing floating-point and integer/fixed- point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic 3203A-3203F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler 3205A-3205F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler 3206A-3206F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core 3201A-3201F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores 3201A-3201F can make use of shared local memory 3208A-3208F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, portions or all of inference and/or training logic 915 may be incorporated into graphics processor 3210. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline 3210, graphics microcontroller 3238, geometry & fixed function pipeline 3214 and 3236, or other logic in FIG.29. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor 3200 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIGS.33A and 33B illustrate thread execution logic 3300 including an array of processing elements of a graphics processor core according to at least one embodiment. FIG.33A illustrates at least one embodiment, in which thread execution logic 3300 is used. FIG.33B illustrates exemplary internal details of an execution unit, according to at least one embodiment. As illustrated in FIG.33A, in at least one embodiment, thread execution logic 3300 includes a shader processor 3302, a thread dispatcher 3304, instruction cache 3306, a scalable execution unit array including a plurality of execution units 3308A-3308N, a sampler 3310, a data cache 3312, and a data port 3314. In at least one embodiment a scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit 3308A, 3308B, 3308C, 3308D, through 3308N-1 and 3308N) based on computational requirements of a workload, for example. In at least one embodiment, scalable execution units are interconnected via an interconnect fabric that links to each of execution unit. In at least one embodiment, thread execution logic 3300 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 3306, data port 3314, sampler 3310, and execution units 3308A-3308N. In at least one embodiment, each execution unit (e.g., 3308A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, array of execution units 3308A-3308N is scalable to include any number individual execution units. In at least one embodiment, execution units 3308A-3308N are primarily used to execute shader programs. In at least one embodiment, shader processor 3302 can process various shader programs and dispatch execution threads associated with shader programs via a thread dispatcher 3304. In at least one embodiment, thread dispatcher 3304 includes logic to arbitrate thread initiation requests from graphics and media pipelines and instantiate requested threads on one or more execution units in execution units 3308A-3308N. For example, in at least one embodiment, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 3304 can also process runtime thread spawning requests from executing shader programs. In at least one embodiment, execution units 3308A-3308N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. In at least one embodiment, execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each of execution units 3308A- 3308N, which include one or more arithmetic logic units (ALUs), is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high- bandwidth register file and associated independent thread-state. In at least one embodiment, execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from memory or one of shared functions, dependency logic within execution units 3308A-3308N causes a waiting thread to sleep until requested data has been returned. In at least one embodiment, while awaiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. In at least one embodiment, each execution unit in execution units 3308A-3308N operates on arrays of data elements. In at least one embodiment, a number of data elements is “execution size,” or number of channels for an instruction. In at least one embodiment, an execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. In at least one embodiment, a number of channels may be independent of a number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 3308A-3308N support integer and floating-point data types. In at least one embodiment, an execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored as a packed data type in a register and execution unit will process various elements based on data size of elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of a vector are stored in a register and an execution unit operates on a vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8- bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible. In at least one embodiment, one or more execution units can be combined into a fused execution unit 3309A-3309N having thread control logic (3307A-3307N) that is common to fused EUs. In at least one embodiment, multiple EUs can be fused into an EU group. In at least one embodiment, each EU in fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to various embodiments. In at least one embodiment, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 3309A-3309N includes at least two execution units. For example, in at least one embodiment, fused execution unit 3309A includes a first EU 3308A, second EU 3308B, and thread control logic 3307A that is common to first EU 3308A and second EU 3308B. In at least one embodiment, thread control logic 3307A controls threads executed on fused graphics execution unit 3309A, allowing each EU within fused execution units 3309A-3309N to execute using a common instruction pointer register. In at least one embodiment, one or more internal instruction caches (e.g., 3306) are included in thread execution logic 3300 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g., 3312) are included to cache thread data during thread execution. In at least one embodiment, a sampler 3310 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 3310 includes specialized texture or media sampling functionality to process texture or media data during sampling process before providing sampled data to an execution unit. During execution, in at least one embodiment, graphics and media pipelines send thread initiation requests to thread execution logic 3300 via thread spawning and dispatch logic. In at least one embodiment, once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 3302 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In at least one embodiment, a pixel shader or fragment shader calculates values of various vertex attributes that are to be interpolated across a rasterized object. In at least one embodiment, pixel processor logic within shader processor 3302 then executes an application programming interface (API)-supplied pixel or fragment shader program. In at least one embodiment, to execute a shader program, shader processor 3302 dispatches threads to an execution unit (e.g., 3308A) via thread dispatcher 3304. In at least one embodiment, shader processor 3302 uses texture sampling logic in sampler 3310 to access texture data in texture maps stored in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing. In at least one embodiment, data port 3314 provides a memory access mechanism for thread execution logic 3300 to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, data port 3314 includes or couples to one or more cache memories (e.g., data cache 3312) to cache data for memory access via a data port. As illustrated in FIG.33B, in at least one embodiment, a graphics execution unit 3308 can include an instruction fetch unit 3337, a general register file array (GRF) 3324, an architectural register file array (ARF) 3326, a thread arbiter 3322, a send unit 3330, a branch unit 3332, a set of SIMD floating point units (FPUs) 3334, and In at least one embodiment a set of dedicated integer SIMD ALUs 3335. In at least one embodiment, GRF 3324 and ARF 3326 includes a set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in graphics execution unit 3308. In at least one embodiment, per thread architectural state is maintained in ARF 3326, while data used during thread execution is stored in GRF 3324. In at least one embodiment, execution state of each thread, including instruction pointers for each thread, can be held in thread-specific registers in ARF 3326. In at least one embodiment, graphics execution unit 3308 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). In at least one embodiment, architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. In at least one embodiment, graphics execution unit 3308 can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter 3322 of graphics execution unit thread 3308 can dispatch instructions to one of send unit 3330, branch unit 3342, or SIMD FPU(s) 3334 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF 3324, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread has access to 4 Kbytes within GRF 3324, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In at least one embodiment, up to seven threads can execute simultaneously, although a number of threads per execution unit can also vary according to embodiments. In at least one embodiment, in which seven threads may access 4 Kbytes, GRF 3324 can store a total of 28 Kbytes. In at least one embodiment, flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures. In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by message passing send unit 3330. In at least one embodiment, branch instructions are dispatched to a dedicated branch unit 3332 to facilitate SIMD divergence and eventual convergence. In at least one embodiment graphics execution unit 3308 includes one or more SIMD floating point units (FPU(s)) 3334 to perform floating-point operations. In at least one embodiment, FPU(s) 3334 also support integer computation. In at least one embodiment FPU(s) 3334 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In at least one embodiment, at least one of FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In at least one embodiment, a set of 8-bit integer SIMD ALUs 3335 are also present, and may be specifically optimized to perform operations associated with machine learning computations. In at least one embodiment, arrays of multiple instances of graphics execution unit 3308 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). In at least one embodiment execution unit 3308 can execute instructions across a plurality of execution channels. In at least one embodiment, each thread executed on graphics execution unit 3308 is executed on a different channel. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, portions or all of inference and/or training logic 915 may be incorporated into execution logic 3300. Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in FIGS.9A or 9B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of execution logic 3300 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. FIG.34 illustrates a parallel processing unit (“PPU”) 3400, according to at least one embodiment. In at least one embodiment, PPU 3400 is configured with machine-readable code that, if executed by PPU 3400, causes PPU 3400 to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, PPU 3400 is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer- readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU 3400. In at least one embodiment, PPU 3400 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as a liquid crystal display (“LCD”) device. In at least one embodiment, PPU 3400 is utilized to perform computations such as linear algebra operations and machine- learning operations. FIG.34 illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of processor architectures contemplated within scope of this disclosure and that any suitable processor may be employed to supplement and/or substitute for same. In at least one embodiment, one or more PPUs 3400 are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, PPU 3400 is configured to accelerate deep learning systems and applications including following non-limiting examples: autonomous vehicle platforms, deep learning, high-accuracy speech, image, text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and more. In at least one embodiment, PPU 3400 includes, without limitation, an Input/Output (“I/O”) unit 3406, a front-end unit 3410, a scheduler unit 3412, a work distribution unit 3414, a hub 3416, a crossbar (“Xbar”) 3420, one or more general processing clusters (“GPCs”) 3418, and one or more partition units (“memory partition units”) 3422. In at least one embodiment, PPU 3400 is connected to a host processor or other PPUs 3400 via one or more high-speed GPU interconnects (“GPU interconnects”) 3408. In at least one embodiment, PPU 3400 is connected to a host processor or other peripheral devices via an interconnect 3402. In at least one embodiment, PPU 3400 is connected to a local memory comprising one or more memory devices (“memory”) 3404. In at least one embodiment, memory devices 3404 include, without limitation, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device. In at least one embodiment, high-speed GPU interconnect 3408 may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs 3400 combined with one or more central processing units (“CPUs”), supports cache coherence between PPUs 3400 and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect 3408 through hub 3416 to/from other units of PPU 3400 such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in FIG.34. In at least one embodiment, I/O unit 3406 is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in FIG.34) over system bus 3402. In at least one embodiment, I/O unit 3406 communicates with host processor directly via system bus 3402 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit 3406 may communicate with one or more other processors, such as one or more of PPUs 3400 via system bus 3402. In at least one embodiment, I/O unit 3406 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communications over a PCIe bus. In at least one embodiment, I/O unit 3406 implements interfaces for communicating with external devices. In at least one embodiment, I/O unit 3406 decodes packets received via system bus 3402. In at least one embodiment, at least some packets represent commands configured to cause PPU 3400 to perform various operations. In at least one embodiment, I/O unit 3406 transmits decoded commands to various other units of PPU 3400 as specified by commands. In at least one embodiment, commands are transmitted to front-end unit 3410 and/or transmitted to hub 3416 or other units of PPU 3400 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in FIG.34). In at least one embodiment, I/O unit 3406 is configured to route communications between and among various logical units of PPU 3400. In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU 3400 for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read/write) by both host processor and PPU 3400 — a host interface unit may be configured to access buffer in a system memory connected to system bus 3402 via memory requests transmitted over system bus 3402 by I/O unit 3406. In at least one embodiment, host processor writes command stream to buffer and then transmits a pointer to start of command stream to PPU 3400 such that front-end unit 3410 receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU 3400. In at least one embodiment, front-end unit 3410 is coupled to scheduler unit 3412 that configures various GPCs 3418 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 3412 is configured to track state information related to various tasks managed by scheduler unit 3412 where state information may indicate which of GPCs 3418 a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit 3412 manages execution of a plurality of tasks on one or more of GPCs 3418. In at least one embodiment, scheduler unit 3412 is coupled to work distribution unit 3414 that is configured to dispatch tasks for execution on GPCs 3418. In at least one embodiment, work distribution unit 3414 tracks a number of scheduled tasks received from scheduler unit 3412 and work distribution unit 3414 manages a pending task pool and an active task pool for each of GPCs 3418. In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC 3418; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs 3418 such that as one of GPCs 3418 completes execution of a task, that task is evicted from active task pool for GPC 3418 and one of other tasks from pending task pool is selected and scheduled for execution on GPC 3418. In at least one embodiment, if an active task is idle on GPC 3418, such as while waiting for a data dependency to be resolved, then active task is evicted from GPC 3418 and returned to pending task pool while another task in pending task pool is selected and scheduled for execution on GPC 3418. In at least one embodiment, work distribution unit 3414 communicates with one or more GPCs 3418 via XBar 3420. In at least one embodiment, XBar 3420 is an interconnect network that couples many of units of PPU 3400 to other units of PPU 3400 and can be configured to couple work distribution unit 3414 to a particular GPC 3418. In at least one embodiment, one or more other units of PPU 3400 may also be connected to XBar 3420 via hub 3416. In at least one embodiment, tasks are managed by scheduler unit 3412 and dispatched to one of GPCs 3418 by work distribution unit 3414. GPC 3418 is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC 3418, routed to a different GPC 3418 via XBar 3420, or stored in memory 3404. In at least one embodiment, results can be written to memory 3404 via partition units 3422, which implement a memory interface for reading and writing data to/from memory 3404. In at least one embodiment, results can be transmitted to another PPU 3404 or CPU via high-speed GPU interconnect 3408. In at least one embodiment, PPU 3400 includes, without limitation, a number U of partition units 3422 that is equal to number of separate and distinct memory devices 3404 coupled to PPU 3400. In at least one embodiment, partition unit 3422 will be described in more detail herein in conjunction with FIG.36. In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU 3400. In at least one embodiment, multiple compute applications are simultaneously executed by PPU 3400 and PPU 3400 provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in form of API calls) that cause driver kernel to generate one or more tasks for execution by PPU 3400 and driver kernel outputs tasks to one or more streams being processed by PPU 3400. In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform task and that exchange data through shared memory. In at least one embodiment, threads and cooperating threads are described in more detail, in accordance with at least one embodiment, in conjunction with FIG.36. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to PPU 3400. In at least one embodiment, deep learning application processor 3400 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by PPU 3400. In at least one embodiment, PPU 3400 may be used to perform one or more neural network use cases described herein. In at least one embodiment, In at least one embodiment, a neuromorphic processor as shown in FIG.35 may be used to implement workers that operate in parallel to train a neural network as described above.as shown in FIG.27 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.35 illustrates c (“GPC”) 3500, according to at least one embodiment. In at least one embodiment, GPC 3500 is GPC 3418 of FIG.34. In at least one embodiment, each GPC 3500 includes, without limitation, a number of hardware units for processing tasks and each GPC 3500 includes, without limitation, a pipeline manager 3502, a pre-raster operations unit (“PROP”) 3504, a raster engine 3508, a work distribution crossbar (“WDX”) 3516, a memory management unit (“MMU”) 3518, one or more Data Processing Clusters (“DPCs”) 3506, and any suitable combination of parts. In at least one embodiment, operation of GPC 3500 is controlled by pipeline manager 3502. In at least one embodiment, pipeline manager 3502 manages configuration of one or more DPCs 3506 for processing tasks allocated to GPC 3500. In at least one embodiment, pipeline manager 3502 configures at least one of one or more DPCs 3506 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 3506 is configured to execute a vertex shader program on a programmable streaming multi-processor (“SM”) 3514. In at least one embodiment, pipeline manager 3502 is configured to route packets received from a work distribution unit to appropriate logical units within GPC 3500, in at least one embodiment, and some packets may be routed to fixed function hardware units in PROP 3504 and/or raster engine 3508 while other packets may be routed to DPCs 3506 for processing by a primitive engine 3512 or SM 3514. In at least one embodiment, pipeline manager 3502 configures at least one of DPCs 3506 to implement a neural network model and/or a computing pipeline. In at least one embodiment, PROP unit 3504 is configured, in at least one embodiment, to route data generated by raster engine 3508 and DPCs 3506 to a Raster Operations (“ROP”) unit in partition unit 3422, described in more detail above in conjunction with FIG.34. In at least one embodiment, PROP unit 3504 is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine 3508 includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, in at least one embodiment, and raster engine 3508 includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for primitive; output of coarse raster engine is transmitted to culling engine where fragments associated with primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to fine raster engine to generate attributes for pixel fragments based on plane equations generated by setup engine. In at least one embodiment, output of raster engine 3508 comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC 3506. In at least one embodiment, each DPC 3506 included in GPC 3500 comprise, without limitation, an M-Pipe Controller (“MPC”) 3510; primitive engine 3512; one or more SMs 3514; and any suitable combination thereof. In at least one embodiment, MPC 3510 controls operation of DPC 3506, routing packets received from pipeline manager 3502 to appropriate units in DPC 3506. In at least one embodiment, packets associated with a vertex are routed to primitive engine 3512, which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM 3514. In at least one embodiment, SM 3514 comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM 3514 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a Single-Instruction, Multiple-Data (“SIMD”) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM 3514 implements a Single-Instruction, Multiple Thread (“SIMT”) architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread and threads executing same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM 3514 are described in more detail herein. In at least one embodiment, MMU 3518 provides an interface between GPC 3500 and memory partition unit (e.g., partition unit 3422 of FIG.34) and MMU 3518 provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 3518 provides one or more translation lookaside buffers (“TLBs”) for performing translation of virtual addresses into physical addresses in memory. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to GPC 3500. In at least one embodiment, GPC 3500 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by GPC 3500. In at least one embodiment, GPC 3500 may be used to perform one or more neural network use cases described herein. In at least one embodiment, a memory partition unit as shown in FIG.36 may be used to implement workers that operate in parallel to train a neural network as described above. FIG.36 illustrates a memory partition unit 3600 of a parallel processing unit (“PPU”), in accordance with at least one embodiment. In at least one embodiment, memory partition unit 3600 includes, without limitation, a Raster Operations (“ROP”) unit 3602; a level two (“L2”) cache 3604; a memory interface 3606; and any suitable combination thereof. Memory interface 3606 is coupled to memory. Memory interface 3606 may implement 32, 64, 128, 1024-bit data buses, or like, for high-speed data transfer. In at least one embodiment, PPU incorporates U memory interfaces 3606, one memory interface 3606 per pair of partition units 3600, where each pair of partition units 3600 is connected to a corresponding memory device. For example, in at least one embodiment, PPU may be connected to up to Y memory devices, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random a36ess memory (“GDDR5 SDRAM”). In at least one embodiment, memory interface 3606 implements a high bandwidth memory second generation (“HBM2”) memory interface and Y equals half U. In at least one embodiment, HBM2 memory stacks are located on same physical package as PPU, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, without limitation, four memory dies and Y equals 4, with each HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, memory supports Single-Error Correcting Double-Error Detecting (“SECDED”) Error Correction Code (“ECC”) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. In at least one embodiment, PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit 3600 supports a unified memory to provide a single unified virtual address space for central processing unit (“CPU”) and PPU memory, enabling data sharing between virtual memory systems. In at least one embodiment frequency of a36esses by a PPU to memory located on other processors is traced to ensure that memory pages are moved to physical memory of PPU that is a36essing pages more frequently. In at least one embodiment, high-speed GPU interconnect 3408 supports address translation services allowing PPU to directly a36ess a CPU’s page tables and providing full a36ess to CPU memory by PPU. In at least one embodiment, copy engines transfer data between multiple PPUs or between PPUs and CPUs. In at least one embodiment, copy engines can generate page faults for addresses that are not mapped into page tables and memory partition unit 3600 then services page faults, mapping addresses into page table, after which copy engine performs transfer. In at least one embodiment, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing available memory. In at least one embodiment, with hardware page faulting, addresses can be passed to copy engines without regard as to whether memory pages are resident, and copy process is transparent. Data from memory 3404 of FIG.34 or other system memory is fetched by memory partition unit 3600 and stored in L2 cache 3604, which is located on-chip and is shared between various GPCs, in a36ordance with at least one embodiment. Each memory partition unit 3600, in at least one embodiment, includes, without limitation, at least a portion of L2 cache associated with a corresponding memory device. In at least one embodiment, lower level caches are implemented in various units within GPCs. In at least one embodiment, each of SMs 3514 may implement a level one (“L1”) cache wherein L1 cache is private memory that is dedicated to a particular SM 3514 and data from L2 cache 3604 is fetched and stored in each of L1 caches for processing in functional units of SMs 3514. In at least one embodiment, L2 cache 3604 is coupled to memory interface 3606 and XBar 3420. ROP unit 3602 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and more, in at least one embodiment. ROP unit 3602, in at least one embodiment, implements depth testing in conjunction with raster engine 3508, receiving a depth for a sample location associated with a pixel fragment from culling engine of raster engine 3508. In at least one embodiment, depth is tested against a corresponding depth in a depth buffer for a sample location associated with fragment. In at least one embodiment, if fragment passes depth test for sample location, then ROP unit 3602 updates depth buffer and transmits a result of depth test to raster engine 3508. It will be appreciated that number of partition units 3600 may be different than number of GPCs and, therefore, each ROP unit 3602 can, in at least one embodiment, be coupled to each of GPCs. In at least one embodiment, ROP unit 3602 tracks packets received from different GPCs and determines which that a result generated by ROP unit 3602 is routed to through XBar 3420. FIG.37 illustrates a streaming multi-processor (“SM”) 3700, according to at least one embodiment. In at least one embodiment, SM 3700 is SM of FIG.35. In at least one embodiment, SM 3700 includes, without limitation, an instruction cache 3702; one or more scheduler units 3704; a register file 3708; one or more processing cores (“cores”) 3710; one or more special function units (“SFUs”) 3712; one or more load/store units (“LSUs”) 3714; an interconnect network 3716; a shared memory/level one (“L1”) cache 3718; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on general processing clusters (“GPCs”) of parallel processing units (“PPUs”) and each task is allocated to a particular Data Processing Cluster (“DPC”) within a GPC and, if task is associated with a shader program, task is allocated to one of SMs 3700. In at least one embodiment, scheduler unit 3704 receives tasks from work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3700. In at least one embodiment, scheduler unit 3704 schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit 3704 manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from plurality of different cooperative groups to various functional units (e.g., processing cores 3710, SFUs 3712, and LSUs 3714) during each clock cycle. In at least one embodiment, Cooperative Groups may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in form of collective group-wide function interfaces. In at least one embodiment, Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. Programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, Cooperative Groups primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. In at least one embodiment, a dispatch unit 3706 is configured to transmit instructions to one or more of functional units and scheduler unit 3704 includes, without limitation, two dispatch units 3706 that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 3704 includes a single dispatch unit 3706 or a37itional dispatch units 3706. In at least one embodiment, each SM 3700, in at least one embodiment, includes, without limitation, register file 3708 that provides a set of registers for functional units of SM 3700. In at least one embodiment, register file 3708 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 3708. In at least one embodiment, register file 3708 is divided between different warps being executed by SM 3700 and register file 3708 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 3700 comprises, without limitation, a plurality of L processing cores 3710. In at least one embodiment, SM 3700 includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores 3710. In at least one embodiment, each processing core 3710, in at least one embodiment, includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores 3710 include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double- precision (64-bit) floating point cores, and 8 tensor cores. Tensor cores are configured to perform matrix operations in accordance with at least one embodiment. In at least one embodiment, one or more tensor cores are included in processing cores 3710. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiply and accumulate operation D = A X B + C, where A, B, C, and D are 4x4 matrices. In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point a37ition with other intermediate products for a 4x4x4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at CUDA level, warp-level interface assumes 16x16 size matrices spanning all 32 threads of warp. In at least one embodiment, each SM 3700 comprises, without limitation, M SFUs 3712 that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs 3712 include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs 3712 include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM 3700. In at least one embodiment, texture maps are stored in shared memory/L1 cache 3718. In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail), in accordance with at least one embodiment. In at least one embodiment, each SM 3700 includes, without limitation, two texture units. Each SM 3700 comprises, without limitation, N LSUs 3714 that implement load and store operations between shared memory/L1 cache 3718 and register file 3708, in at least one embodiment. Each SM 3700 includes, without limitation, interconnect network 3716 that connects each of functional units to register file 3708 and LSU 3714 to register file 3708 and shared memory/ L1 cache 3718 in at least one embodiment. In at least one embodiment, interconnect network 3716 is a crossbar that can be configured to connect any of functional units to any of registers in register file 3708 and connect LSUs 3714 to register file 3708 and memory locations in shared memory/L1 cache 3718. In at least one embodiment, shared memory/L1 cache 3718 is an array of on-chip memory that allows for data storage and communication between SM 3700 and primitive engine and between threads in SM 3700, in at least one embodiment. In at least one embodiment, shared memory/L1 cache 3718 comprises, without limitation, 128KB of storage capacity and is in path from SM 3700 to partition unit. In at least one embodiment, shared memory/L1 cache 3718, in at least one embodiment, is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache 3718, L2 cache, and memory are backing stores. Combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses, in at least one embodiment. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. Integration within shared memory/L1 cache 3718 enables shared memory/L1 cache 3718 to function as a high- throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data, in accordance with at least one embodiment. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, creating a much simpler programming model. In general purpose parallel computation configuration, work distribution unit assigns and distributes blocks of threads directly to DPCs, in at least one embodiment. In at least one embodiment, threads in a block execute same program, using a unique thread ID in calculation to ensure each thread generates unique results, using SM 3700 to execute program and perform calculations, shared memory/L1 cache 3718 to communicate between threads, and LSU 3714 to read and write global memory through shared memory/L1 cache 3718 and memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM 3700 writes commands that scheduler unit 3704 can use to launch new work on DPCs. In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices such as additional PPUs, memory, a reduced instruction set computer (“RISC”) CPU, a memory management unit (“MMU”), a digital-to-analog converter (“DAC”), and like. In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. Graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated graphics processing unit (“iGPU”) included in chipset of motherboard. Inference and/or training logic 915 are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic 915 are provided herein in conjunction with FIGS.9A and/or 9B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to SM 3700. In at least one embodiment, SM 3700 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by SM 3700. In at least one embodiment, SM 3700 may be used to perform one or more neural network use cases described herein. In at least one embodiment, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. In at least one embodiment, multi- chip modules may be used with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (“CPU”) and bus implementation. In at least one embodiment, various modules may also be situated separately or in various combinations of semiconductor platforms per desires of user. In at least one embodiment, computer programs in form of machine-readable executable code or computer control logic algorithms are stored in main memory 1504 and/or secondary storage. Computer programs, if executed by one or more processors, enable system 1500 to perform various functions in accordance with at least one embodiment. Memory 1504, storage, and/or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (“DVD”) drive, recording device, universal serial bus (“USB”) flash memory, etc. In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of CPU 1502; parallel processing system 1512; an integrated circuit capable of at least a portion of capabilities of both CPU 1502; parallel processing system 1512; a chipset (e.g., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.); and any suitable combination of integrated circuit(s). In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and more. In at least one embodiment, computer system 1500 may take form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic. In at least one embodiment, parallel processing system 1512 includes, without limitation, a plurality of parallel processing units (“PPUs”) 1514 and associated memories 1516. In at least one embodiment, PPUs 1514 are connected to a host processor or other peripheral devices via an interconnect 1518 and a switch 1520 or multiplexer. In at least one embodiment, parallel processing system 1512 distributes computational tasks across PPUs 1514 which can be parallelizable — for example, as part of distribution of computational tasks across multiple graphics processing unit (“GPU”) thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and/or write access) across some or all of PPUs 1514, although such shared memory may incur performance penalties relative to use of local memory and registers resident to a PPU 1514. In at least one embodiment, operation of PPUs 1514 is synchronized through use of a command such as __syncthreads(), wherein all threads in a block (e.g., executed across multiple PPUs 1514) to reach a certain point of execution of code before proc15ding. Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit disclosure to specific form or forms disclosed, but on contrary, intention is to cover all modifications, alternative constructions, and equivalents falling within spirit and scope of disclosure, as defined in appended claims. At least one embodiment can be described in view of at least one of following clauses: 1. A processor comprising: two or more processing cores to train portions of a neural network separately in parallel. 2. A processor of clause 1, wherein the two or more processing cores apply one or more gradients to different sets of nodes of the neural network. 3. The processor of clause 1 or 2, where in the neural network is trained, at least in part, by generating a weight update by combining a plurality of a partial weight updates produced in parallel by the two or more processing cores. 4. The processor of any of clauses 1-3, wherein the processor further divides a weight update operation into a plurality of partial weight update operations and distributes individual partial weight update operations to the two or more processing cores. 5. The processor of clause 4, wherein the partial weight update operations are produced by dividing an initial weight and gradient update into a plurality of distinct portions. 6. The processor of clause 4 or 5, wherein each partial weight update is executed using a different thread. 7. The processor of any of clauses 4-6, wherein the processor further gathers the partial weight updates to produce the weight update. 8. A system, comprising: one or more processors to train portions of a neural network separately in parallel; and one or more memories to store the neural network. 9. The system of clause 8 where in the neural network is trained, at least in part, by: generating a plurality of partial weight updates in parallel using the one or more processors; and combining the plurality of partial weight updates to produce a weight gradient update. 10. The system of clause 9, wherein the plurality of partial weight updates is produced in parallel using a plurality of worker threads. 11. The system of clause 9 or 10, wherein the neural network is trained at least in part by: forwarding propagating an input through the neural network to produce an output; determining an error based at least in part on a difference between the output and an expected value; and backpropagating the error to determine a gradient, the plurality of partial weight updates based at least in part on the gradient. 12. The system of any of clauses 9-11, wherein the plurality of partial weight updates are produced at least by: identifying a plurality of subsets of network nodes of the neural network; and producing a partial weight update for each subset in the plurality of subsets. 13. The system of clause 12, wherein the plurality of subsets are non-overlapping subsets of weights of the neural network. 14. The system of clause 12 or 13, wherein: an individual subset of the plurality of subsets includes a quantity of node weights; and the quantity of node weights is determined based at least in part on an amount of processing power available to a worker assigned to process the individual subset relative to other workers assigned to process other subsets. 15. The system of any of clauses 8-14, wherein: the system determines a set of gradients for each input of a set of input values; the set of gradients is distributed to each of the one or more processors. 16. A method, comprising training a neural network by, at least in part, training different portions of a neural network separately in parallel using a plurality of processors. 17. The method of clause 16 wherein: the neural network is trained at least in part by distributing gradient information to the plurality of workers; the workers calculate different portions of a weight update in parallel; and the different portions are aggregated to produce new weight values of the neural network. 18. The method of clause 17, wherein the neural network is trained at least in part by: forwarding propagating an input through the neural network to produce an output; determining an error based at least in part on the output; and determining a gradient by at least backpropagating the error, the different portions of the weight updates based at least in part on the gradient. 19. The method of clause 18, wherein: the gradient is distributed to each of the plurality of workers; and the plurality of workers calculate the different portions of the weight update. 20. The method of any of clauses 16-19, wherein each worker of the plurality of workers executes on a different processor. 21. The method of any of clauses 16-20, wherein each worker of the plurality of workers executes in parallel on a graphical processing unit. 22. The method of clause 17, wherein a number of different portions of the weight update matches a number of available processors of a computer system. 23. The method of any of clauses 17-22, wherein the weight update is divided into substantially equal no overlapping groups of node weights to produce the different portions. 24. A speech processing system comprising a neural network that takes a digital representation of sound as input and identifies elements of human speech, portions of the neural network trained to recognize human speech separately in parallel by a plurality of processes. 25. The speech processing system of clause 24 wherein the neural network: generates a plurality of weight updates in parallel; and combines the plurality of weight updates into a single weight update. 26. The speech processing system of clause 24 or 25, wherein the speech processing system further comprises one or more processors and memory to store executable instructions that, as a result of being executed by the one or more processors, cause the speech processing system to at least: obtain data representing audio from a microphone; process the data using the neural network to identify a spoken word represented in the data; and perform an action based at least in part on the identity of the spoken word. 27. The speech processing system of clause 26, wherein the action is a navigation request to be processed by a navigation system of a vehicle. Use of terms “a” and “an” and “the” and similar referents in context of describing disclosed embodiments (especially in context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within range, unless otherwise indicated herein and each separate value is incorporated into specification as if it were individually recited herein. Use of term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, term “subset” of a corresponding set does not necessarily denote a proper subset of corresponding set, but subset and corresponding set may be equal. Conjunctive language, such as phrases of form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of set of A and B and C. For instance, in illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). Number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, phrase “based on” means “based at least in part on” and not “based solely on.” Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non- transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause computer system to perform operations described herein. Set of non-transitory computer-readable storage media, in at least one embodiment, comprises multiple non- transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of code while multiple non-transitory computer-readable storage media collectively store all of code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors — for example, a non-transitory computer- readable storage medium store instructions and a main central processing unit (“CPU”) executes some of instructions while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of instructions. Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations. Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of disclosure and does not pose a limitation on scope of disclosure unless otherwise claimed. No language in specification should be construed as indicating any non-claimed element as essential to practice of disclosure. All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein. In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may be not intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system’s registers and/or memories into other data similarly represented as physical quantities within computing system’s memories, registers or other such information storage, transmission or display devices. In a similar manner, term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, “processor” may be a CPU or a GPU. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously or intermittently. Terms “system” and “method” are used herein interchangeably insofar as system may embody one or more methods and methods may be considered a system. In present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. Process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In another implementation, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. References may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or interprocess communication mechanism. Although discussion above sets forth example implementations of described techniques, other architectures may be used to implement described functionality, and are intended to be within scope of this disclosure. Furthermore, although specific distributions of responsibilities are defined above for purposes of discussion, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances. Furthermore, although subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.
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