DYNAMIC REGISTER WITH LOW CLOCK RATE TESTING CAPABILITY

Title:

DYNAMIC REGISTER WITH LOW CLOCK RATE TESTING CAPABILITY

Document Type and Number:

WIPO Patent Application WO2000028341

Kind Code:

A3

Abstract:

A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the ouput terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Inventors:

HATAMIAN MEHDI (US)

Application Number:

PCT/US1999/026482

Publication Date:

November 09, 2000

Filing Date:

November 09, 1999

Export Citation:

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Assignee:

BROADCOM CORP (US)
HATAMIAN MEHDI (US)

International Classes:

G01R31/30; G01R31/317; G01R31/3185; H04B3/23; H04B3/32; H04L1/00; H04L1/24; H04L7/02; H04L7/033; H04L25/03; H04L25/06; H04L25/14; H04L25/49; H04L25/497; (IPC1-7): G01R31/3185

Foreign References:

US5008618A

1991-04-16

Other References: