AND UTILIZING SAME

This application is a continuation-in-part of International Patent

Application No. PCT/US89/05882 filed December 27, 1989, which in turn is a continuation-in-part of United States Patent Application Serial No.290,468 filed

December 27, 1988, the subject matter of both applications being incorporated herein by reference thereto.

Technical Field

The invention relates to bipolar three-terminal gated diodes; memory matrices including such diodes; neural synaptic networks including such diodes;

DRAM (Dynamic Random Access Memory) units including such diodes; bipolar transistors; a JFET (Junction Field Effect Transistor) using such diode; GaAs and AlGaAs heterostructures; and methods of constructing and utilizing same.

Relevant Art The prior art is exemplified by the text "Physics and Technology of

Semiconductor Devices" by A. S. Grove, copyright 1967 by John Wiley & Sons,

Inc., the subject matter of which is incorporated herein by reference thereto.

The relevant, but not prior, art is exemplified by an article entitled

"Ferroelectric Materials For 64 Mb and 256 Mb DRAMs" by Laureen H. Parker and Al F. Tasch appearing in the January 1990 issue of IEEE CIRCUITS AND

DEVICES MAGAZINE, the entire contents of which is incorporated herein by reference thereto.

Disclosure of Invention

A first embodiment of the invention provides an electronic device, comprising at least one first semiconductor portion comprising a first predetermined type of semiconductor material, and at least one second semiconductor portion comprising a second predetermined type of semiconductor material. At least a part of the second portion is contiguous with at least a part of the first portion. At least one insulator portion is contiguous with at least a part of the first and second portions. There is also included at least one metallic portion, and at least one ferroelectric portion having at least

a part thereof disposed between at least a part of the insulator portion and a part of the metallic portion.

A second embodiment provides an electronic device as described above, but wherein the insulator, ferroelectric and first metallic portions form a gate assemblage having at least one aperture therein. There is also provided at least one second metallic portion within the aperture and contiguous with at least a part of the insulator portion. The second metallic portion is contiguous with at least a part of the second semiconductor portion.

A third embodiment provides a memory matrix comprising a plurality of bipolar three-terminal gated diodes which are reverse-biased, and wherein each diode takes the form of the electronic devices described herein.

Another embodiment provides a neural synaptic network comprising a plurality of bipolar three-terminal gated diodes which take the form of the electronic devices described herein. Another embodiment provides a DRAM which uses the high dielectric constant of a ferroelectric and/or an insulator for dynamic storage without fully switching the ferroelectric from one polarization state to the other, and also uses a p-n junction as a "pass-gate" in an array.

Another embodiment provides a bipolar transistor wherein the electronic device described herein can be incorporated as a junction in a npn or pnp bipolar transistor, either as a base, a collector or an emitter junction.

Another embodiment provides a structure which uses the gated diode ensemble in a ferroelectric controlled p-n junction in a JFET.

Another embodiment provides a structure wherein the electronic device described herein is used in GaAs and AlGaAs heterostructures.

A further embodiment provides a ferroelectric gated diode which can be addressed by applying light to the ferroelectric.

Fig. 1 is a schematic view of an electronic device according to a first embodiment. Fig. 2 is a schematic view of an electronic device according to a second embodiment.

Fig. 3 shows a top view of the Fig. 2 device.

Fig. 4 is applicant's proposed symbol for a ferroelectric gated diode. Fig. 5 shows a neural network according to the invention. Fig. 6 is applicant's symbol for a neuron assemblage as representing the elements enclosed in phantom line in Fig. 5. Fig. 7 shows a neural synaptic network according to the invention.

Fig. 8 shows a plot of total junction capacitance as a function of the gate voltage.

Fig. 9 shows another embodiment wherein the electronic device is used in GaAs and AlGaAs heterostructures. Fig. 10 shows a memory matrix according to the invention.

Fig. 11 shows a device having the gate trenched in the semiconductor portion.

Electronic devices described herein can be fabricated using the machines, techniques and methods disclosed in International Patent Application No. PCT/US89/05882 and U. S. Patent Application Serial No. 290,468.

Fig. 1 shows electronic device 1 having first and second semiconductor portions 2 and 3. Ferroelectric portion 5 is sandwiched between insulator 4 and first metallic portion 6. Preferably, but not necessarily, portion 4 is comprised of yttrium oxide, CaF ₂ , BaF ₂ , Ta^, Si0 ₂ , Si ₃ N ₄ , or other linear dielectric silicon compounds which may be deposited and epitaxially regrown on Si, GaAs or InP semiconductors. Portion 4 may comprise a ferroelectric material which may or may not be the same as the material of portion 5.

The assemblage of portions 4, 5 and 6 form a gate structure which is contiguous with a part of portions 2 and 3 and straddles the portions 3. First terminal 7 is electrically connected to portion 2. Second terminal

V _j is connected to portion 3. Third terminal V _G is electrically connected to portion 6.

Portion 3 comprises a region of relatively high impurity or doping concentration. Depletion region 8 forms around portion 3. Portion 5 interacts with the electrical charge volume of region 8 by way of semiconductor surface modulation of region 8 or conductivity modulation.

The term ferroelectric material as used herein is intended to include, but

is not limited to, the fluoride family such as BaMnF^ BaMgF ₂ , etc., KN0 ₃ , and materials having a general composition of AB0 ₃ , such as PbTi0 ₃ , Pb _j Zr _y TiOa, Pb _x La _y Z^TK , and YMn0 ₃ , where Y can be any of the rare earth elements.

Figs. 2 and 3 show a second embodiment in the form of device 18 having first and second semiconductor portions 9 and 10. Gate assemblage 19 is formed by ferroelectric portion 12 sandwiched between insulator portion 11 and first metallic portion 13. Assemblage 19 has an opening 15. Portion 10, which comprises a region of relatively high doping concentration, straddles opening 15 to contact diametrically opposed portions of portion 11. Preferably, but not necessarily, portion 11 is comprised of yttrium oxide, or of the other materials discussed above in relation to Fig. 1.

Second metallic portion 14 is disposed within opening 15 and is contiguous with a part of portions 10 and 11.

First terminal 17 is electrically connected to portion 9. Second terminal V _j is electrically connected to portion 14. Third terminal V _G is electrically connected to portion 13.

Depletion region 16 is formed between portions 9 and 10. Portion 12 interacts with the electrical charge volume of region 16 via semiconductor surface modulation of region 16 or conductivity modulation. Portion 5 or 12 is used to establish the level of leakage of the pn junction via extension of region 8 or 16, and an increase in current caused by thermal generation of carriers in region 8 or 16.

The invention also contemplates a device wherein the ferroelectric portion is used to establish a capacitance level of the pn junction via the ferroelectric spontaneous polarization charge modulation of the total depletion region volume, including the depletion under the gated region.

The device can also be used for DRAM architecture wherein the device uses the high dielectric constant of the ferroelectric and/or insulator for dynamic storage without fully switching the ferroelectric from one polarization state to the other, and/or use of the pn junction as a "pass-gate" in an array.

The inventive device can also be used for constructing a bipolar transistor. The device can be incorporated as a junction in a npn or pnp bipolar

transistor, either as a base, a collector or an emitter junction. The preferred configuration would be the base-collector junction by which the gain of the transistor is controlled by the state of the ferroelectric.

The inventive device can also be used for fabricating a new type of JFET. The device would use the gated diode ensemble as a ferroelectric controlled pn junction in a configuration known as a JFET, wherein the ferroelectric gated diode is the gate junction.

Fig. 4 illustrates a proposed symbol 20 for the ferroelectric gated diode according to the invention. The ferroelectric portion is designated by the reference number 21. The symbol 20 is used below in the explanation of the neural network 22.

Fig. 5 shows network 22 composed of a ferroelectric gated diode or synaptic weight 20 connected to a neuron portion 23. The neuron portion 23 is enclosed in phantom lines. Fig. 6 presents a symbol 23 for showing the neuron portion of network

22.

Fig. 7 illustrates a neural synaptic network 30 having X-decoders 31, 32, 33 and 34 which are connected to neurons 35, 36, 37 and 38.

Network 30 includes Y-decoders 39, 40, 41 and 42 which are connected, substantially transverse to the X-decoders, to neurons 43, 44, 45 and 46. Network 30 has typical synaptic weights 47 and 48 connected therein.

The diode in its various configurations, including the optical configuration described below, can be used as the "weighted synaptic matrix" in neural networks. Such networks employ operational amplifiers, resistors, and capacitors to form an "analog storage" associative memory. The ferroelectric gated diode is essentially a programmable synaptic weight which can be set to a certain value during an interaction of a program being processed by such a neural network.

The invention contemplates an optical configuration wherein the ferroelectric-gated diode can be addressed by applying light to the ferroelectric. The metallic gate should be transparent which can be achieved by various techniques, such as using either thin metallic film or using an indium tin oxide transparent electrode. When used in this configuration, the pyroelectric, as well

as the ferroelectric, properties of the ferroelectric material are utilized. Such a device can be used for optically-read memories, infrared detectors, an optical memory, and a thermal imaging device using a matrix.

With reference to Figs. 1-4, the ferroelectric portion may be used to establish a capacitance level of the pn junction by way of the ferroelectric spontaneous polarization P _s charge modulation of the total depletion region volume including the depletion under the gated region.

Fig. 8 shows a plot wherein the abscissa represents the gate voltage V _G which is equivalent to APg/Cp, where P _s is the spontaneous polarization of the ferroelectric, A is the area of the gate, and C _F is the ferroelectric gate capacitance.

In Fig. 8 the ordinate represents the total junction or diode capacitance. Point 1 along the abscissa V _G represents point 2 represents The capacitance is modulated by voltage or the spontaneous polarization of the ferroelectric.

Fig.9 shows another embodiment in the form of a high electron mobility transistor (HEMT) 50. HEMT 50 includes a metal portion 51, a ferroelectric portion 52, an AlGaAs portion 53 which in this case serves as the insulator portion, a gallium arsenide buffer layer 54, and a gallium arsenide portion 56. Portion 55 represents the two dimensional electron gas.

The Fig. 9 device, when used in the gallium arsenide and AlGaAs heterostructure, modulates gas 55 in the configuration known as the high electron mobility transistor. With the ferroelectric gate, HEMT 50 becomes a storage cell for high speed memories. Fig. 10 shows a memory matrix 60 having row decoders 61 electrically connected to sense amplifiers and X-output buffers 62. Column decoders 63 are electrically connected to sense amplifiers and Y-output buffers 64. Interconnected in the array are ferroelectric gated diodes 67.

Matrix 60 has read enable and write enable circuits 65, and gate control circuits 66. In the matrix array, it is preferable to have the diodes 67 reverse- biased.

The n-type regions and p-type regions shown in Figs. 1 and 2 may be

reversed.

Fig. 11 shows a device similar to Fig. 1, but in which the ferroelectric gate assemblage, including the metallic, the ferroelectric, and the insulator portions, is trenched within the first semiconductor portion, and in which the second semiconductor portion includes first and second portions disposed on opposite sides of the trenched assemblage. As with the Fig. 1 device, a region of the second semiconductor portion (the first second semiconductor portion) has a relatively high doping concentration.

The above description is intended to be illustrative only, and not limiting.