Background A frequent requirement of power supplies is that they be capable of being paralleled, i. e., where the outputs of two or more power supplies are connected together in parallel to serve a common output load. In such an arrangement, it is usually critical that the failure of any one power supply must not cause the failure of either the common output load, or of any of the other respective paralleled supplies.

For example, such a requirement may arise in a "modular system,"where individual power supply modules are connected together in parallel in order reach a desired output power level--i. e., beyond that which can be supported by a single module. Such a requirement may also exist in a redundant system, where critical output loads must be supported even if a single power supply module fails.

An established method for paralleling two or more individual power supplies is to use an"or'ring diode"to connect each respective power supply to the load. For example, as seen in FIG. 1, a plurality of individual power supplies 22-24 may be connected to a common output load 26 by way of respective or'ring diodes 28-30. The or'ring diodes 28-30 provide protection if any one power supply 22-24 fails, since they prevent current from flowing"upstream"from the remaining power supplies.

However, the or'ring diodes 28-30 impose a substantial forward voltage drop and, thus, output power

loss to the load 26, equal to approximately Vf/VoUtI where Vf is the voltage across the respective or'ring diode and Vont is the common load voltage. For example, if a 12v output is required from a respective power supply module and Vf was at 1 volt, the anode voltage of its respective or'ring diode would be 13v, with a respective forward loss of 1/13 = 7. 7% in system efficiency. Although lower output voltage requirements may allow for relatively low loss schottky diodes to be employed as or'ring diodes, these are limited to a forward voltage drop of approxi- mately 0.3 to 0.4 volts. By way of example, a 3.3 volt output through a shottky diode still results in a system efficiency loss range of approximately 9%.

A further problem with or'ring diodes is their negative temperature coefficient. In particular, as the diode temperature increases with current, its forward voltage decreases. As a result, the or'ring diodes are difficult to parallel for a single power supply module, which may otherwise prove useful in order to reduce the overall losses.

For example, as seen in FIG. 2, a pair of or'ring diodes 34 and 36 are paralleled to connect a single power supply module 32 to a common load 38, along with one or more other parallel power supplies (not shown). At first glance, this would appear to reduce the forward voltage drop. However, even if diodes 34 and 36 are selected to have the"same"Vf, in practice, one of the diodes will begin to conduct more current than the other. As this happens, the diode conducting a greater amount of current will heat up faster than the other, causing its respective forward voltage to decrease faster and, thus, the diode will conduct even more current, until it is carrying the entire load from the power supply 32 to the load 38.

As a practical matter, therefore, it is necessary to have each respective or'ring diode capable of carrying the full current flow of a respective power supply it connects to a common load.

Summary of the Invention The present invention overcomes the disadvantages of prior art diode or'ring circuits, by employing field effect transistors ("FETs"), such as metal-oxide- semiconductor FETS ("MOSFETs"), in or'ring circuits, in order to more efficiently parallel two or more power supplies serving a common load.

In a preferred embodiment, each power supply of a parallel system is connected to a common load by way of an "or'ring MOSFET"switch, wherein a source terminal of the MOSFET is connected to the power supply, and a drain terminal of the MOSFET is connected to the load, respect- ively, such that a characteristic body diode of the MOSFET has its anode connected to the power supply and its cathode connected to the load. In accordance with a first aspect of the present invention, a channel gate of the MOSFET is controlled by a feedback circuit including a first differential amplifier, which eliminates the common mode voltage between the respective source and drain terminals of the MOSFET switch, and amplifies the remain- ing voltage differential, wherein the amplified differen- tial signal is applied to the MOSFET gate. In selected preferred embodiments, a further differential amplifier may be used to increase the output gain on the voltage differential signal in order to increase the incremental sensitivity of the feedback control circuit on the MOSFET gate channel.

In operation, as current initially begins to flow from the respective power supply to the load, the ampli- fied differential voltage signal remains below a threshold gate voltage of the MOSFET, and the current is restricted to the forward biased body diode channel in order to pass through to the load. As the voltage differential across the respective MOSFET source and drain terminals begins to grow, however, the amplified differential signal reaches the linear region of the MOSFET threshold gate voltage, thereby allowing current to begin flowing through the main

MOSFET channel, shorting out the body-diode channel. The increased current flow, in turn, continues to increase the differential voltage across the MOSFET, until the ampli- fied differential signal rises above the linear region, and the MOSFET gate channel is fully ON.

At least one advantage of this arrangement is that the forward voltage drop through the MOSFET switch can be arbitrarily small, since the dependence on the body-diode channel to pass current through the MOSFET is minimal. At the same time, the biasing of the body-diode of the MOSFET prevents current from passing upstream from the load to the respective power supply, e. g., should the power supply fail.

In accordance with yet another aspect of the present invention, because FETs generally have a positive tempera- ture coefficient, two or more MOSFETs may be paralleled to connect the output of a single power supply to a common load, thereby decreasing the net"ON-resistance"of the respective MOSFET body-diode channel (s), while not requir- ing that a single FET be able to carry the entire current load from a respective supply.

As will be apparent to those skilled in the art, other and further objects and advantages will appear hereinafter.

Brief Description of the Drawings The drawings illustrate both the design and utility of preferred embodiments of the present invention, in which: FIG. 1 is a schematic diagram of a prior art diode- based or'ring circuit for paralleling multiple power supplies serving a common load; FIG. 2 is a schematic diagram,, illustrating the use of multiple, paralleled or'ring diodes to connect a single power supply to a load;

FIG. 3 is a schematic diagram of a first preferred embodiment of a FET-based or'ring circuit for paralleling multiple power supplies serving a common load; and FIG. 4 is a schematic diagram of a second preferred embodiment of a FET-based or'ring circuit for paralleling multiple power supplies serving a common load.

Detailed Description of the Preferred Embodiments Referring to FIG. 3, in a preferred modular power supply system (not shown in its entirety), a given power supply 42 is connected to a common load 44 through a power MOSFET 46. The power MOSFET 46 includes a source terminal 48 connected to the power supply 42, and a drain terminal 50 connected to the load 44, respectively. By this configuration, a characteristic body diode 54 of MOSFET 46 has its anode connected to the power supply 42 and its cathode connected to the load 44. The MOSFET 46 also includes a gate terminal 56 that, when"closed,"allows current to pass from the source terminal 48 to the drain terminal 50 through a main MOSFET channel 58.

In particular, if a selected threshold voltage is applied to the gate terminal 56, the gate closes and current is allowed to conduct through the main MOSFET channel 58. Generally speaking, if less than this threshold voltage is applied to the gate terminal 56, the gate will remain"open,"and current cannot flow through channel 58. In accordance with a known physical property of MOSFETs, however, the threshold gate voltage includes a"linear region,"in which the gate 56 will linearly move from zero-to-full current conduction through channel 58.

In accordance with one aspect of the present invention, the MOSFET gate terminal 56 is controlled by a pair of amplifiers, 60 and 62, respectively, as follows: A first electrical lead 64 connects the MOSFET source terminal 48 to a positive input terminal 66, and a second electrical lead 68 connects the MOSFET drain terminal 50 to a negative input terminal 70, respectively, of ampli-

fier 60, wherein amplifier 60 removes the common mode voltage between the respective source and drain terminals and amplify the remaining difference. In order to set the amplification gain through amplifier 60, the following resistances are added: a resistor 52 having a selected resistance value R1 is inserted across lead 64 between the power supply 42 and the positive amplifier input terminal 66; a resistor 53 also having a resistance value R1 is inserted across lead 68 between the load 44 and the nega- tive amplifier input terminal 70; a resistor 55 having a second selected resistance value R2 is inserted across a ground path 72 connected to the positive amplifier input terminal 66; and a resistor 57 also having resistance value R2 is inserted across a feedback loop 74, which connects the output 76 of amplifier 60 to the negative input terminal 70, respectively. In this manner, ampli- fier 60 amplifies the voltage differential between the respective MOSFET source and drain terminals 48 and 50 by a factor of R2/R1, while rejecting the common mode voltage.

The output 76 of the amplifier 60 is then fed into a positive input terminal 78 of amplifier 62, which is configured as a pure gain stage amplifier. In particular, a feedback loop 84 connects the output 80 of amplifier 62 to a negative input terminal 82. In order to set the gain of amplifier 62, a resistor 81 having a third selected resistance value R3 is inserted across the feedback loop 84, and a resistor 83 having a fourth selected resistance R4 is inserted across a path to ground connected to negative input terminal 82, respectively, wherein the gain through amplifier 62 is equal to 1 + R3/R4.

The output 80 of the ("gain") amplifier 62, which represents the (twice) amplified voltage differential between the respective source and drain terminals 48 and 50 of MOSFET 46, is then applied to the MOSFET gate terminal 56. A selected gate resistor 84 is inserted across the output signal 80 in order to limit the amount of current required to apply the threshold voltage to the

gate terminal 56, as well as to help prevent ON/OFF oscillations of the gate 56.

For purposes of illustration and to better understand the invention, the process for initially connecting the power supply 42 to the common load 44 is as follows: When the power supply 42 is OFF, no current is flow- ing through the MOSFET 46 and, thus, there is no voltage differential detected by amplifier 60, whose output 76 is zero. Accordingly, the output 80 of the gain amplifier 62 is also zero, and the MOSFET gate terminal 56 will remain fully open. As an initial (relatively small) amount of current begins to flow from the power supply 42 during an initial start-up, although the MOSFET channel 58 does not conduct, this current will be able to flow through the forward biased body diode channel 54, thereby causing a voltage differential to develop between the respective source and drain terminals, 48 and 50. This voltage differential is detected by amplifier 60, which removes the common mode voltage, and amplifies the difference by a factor of R2/R1. The gain amplifier 62 will further amplify the voltage differential signal by a factor of 1 + R3/R4, wherein its output voltage signal 80 is applied to the gate terminal 56, via the gate resistor 84.

Initially, only the body-diode channel 54 will conduct current. However, after only a brief current ramp-up, the amplified voltage differential will reach the linear region of gate terminal 56, and the MOSFET channel 58 begins to conduct current. As the current begins to flow through the channel 58, the body diode 54 is shorted out, and almost all current flows through channel 58. As the current level continues to increase, the voltage dif- ferential across the respective source and drain terminals 48 and 50 also continues to increase until, ultimately, the gate terminal 56 is fully closed (or"enhanced") and the MOSFET channel 58 is fully ON. At this point, any forward voltage drop produced across the MOSFET 46 is dependent only on the MOSFET channel 58"ON-resistance,"

which is relatively insignificant, when compared to the losses through the prior art or'ring diode circuits.

In particular, an advantage of using the MOSFET-based or'ring circuit configuration of FIG. 3 is that it depends very little on the MOSFET's body diode 54--i. e., once the current begins flowing from the power supply 42 to the load 44, the MOSFET channel 58 is activated by the differ- ential gain amplification process. If the power supply 42 fails, or if the load voltage 44 is higher than the converter's output (e. g., where another power supply in the system is regulating at a higher voltage), the MOSFET channel 58 is OFF, and the body diode 54 is reversed biased, thus blocking current from flowing"backwards" into the power supply 42 from the other power supplies (not shown) connected to load 44.

Importantly, the forward drop through the MOSFET 46 can be advantageously small. For example, based on tests conducted by the present inventor, at 1 amp delivered across a 10 m0 MOSFET, the forward drop is only 10 mV, i. e., only an approximate 0.1% penalty in a 12 volt system.

Further, because MOSFETs have a positive temperature coefficient, an advantage of the present invention is that more than one MOSFET can be used to connect the power supply 42 to the load 44. In particular, two or more MOSFETs can be controlled by a single differential voltage control (e. g., such as amplifiers 60 and 62), wherein the MOSFETs are paralleled in order to reduce the overall net channel ON-resistance, and thereby increase the overall system efficiency. In practice, this will be a design choice dependent upon the cost trade-off of adding further MOSFETs, along with the corresponding afore-described control circuitry, versus the efficiency gained by reduc- ing the net forward voltage system loss. In such a multiple or'ring MOSFET configuration, it is thus unneces- sary to have a single device capable of carrying the entire current.

Still further, with the teachings set forth herein, it should also be readily apparent to those skilled in the art that the gain amplifier 62 may be omitted from the gate control circuit of FIG. 3, if the output signal from the first amplifier 60 is adequate to control the MOSFET gate 56 threshold voltage through the respective linear region.

Referring to FIG. 4, a second preferred embodiment includes yet another given power supply 92 within a or'ring arrangement, which is alternately connected to a common load 94 by a power MOSFET 96. The power MOSFET 96 includes a source terminal 98 connected to the power supply 92 and a drain terminal 100 connected to the load 94, respectively, such that a characteristic body diode 104 of MOSFET 96 has its anode connected to the power supply 92 and its cathode connected to the load 94. The MOSFET 96 also includes a gate terminal 106 that, when "closed,"allows current to pass from the source terminal 98 to the drain terminal 100 through a main MOSFET channel 108.

As with the MOSFET 46, if a selected threshold volt- age is applied to the gate terminal 106 of MOSFET 96, the gate closes and current is allowed to conduct through the main channel 108. If less than this threshold voltage is applied to the gate terminal 106, it will remain"open." The gate voltage of gate 106 includes a linear region, wherein the gate will linearly move from zero-to-full current conduction through the MOSFET channel 108.

In accordance with yet another aspect of the present invention, the MOSFET gate terminal 106 of MOSFET 96 is controlled by a configuration of three amplifiers, 110, 112 and 114, respectively, as follows: A first electrical lead 102 connects the MOSFET source terminal 98 to a positive input terminal 116 of amplifier 110, and a second electrical lead 118 connects the MOSFET drain terminal 100 to a positive input terminal 120 of amplifier 112, respectively, wherein respective

outputs 122 and 124 of amplifiers 110 and 112 are con- nected to a common feedback path 126. The common feedback path 126 includes a first node"A"which connects an electrical path 128 to a negative input terminal 130 of amplifier 112, and a second node"B"which connects an electrical path 132 to a negative input terminal 134 of amplifier 110, respectively. The common feedback path 126 also includes a first resistor 136 having a selected resistance value R5 interposed between output 124 and node "A" ; a second resistor 138 having a selected resistance value of R6 interposed between node"A"and node"B" ; and a third resistor 140 also having a resistance value of R5 interposed between node"B"and output 122, respectively.

Output 124 of amplifier 112 is connected across a resistor 142 having a resistance value of R, to a third node"C", and output 122 of amplifier 110 is connected across a resistor 144, which also has a resistance value of R, to a fourth node"D", respectively. Node"C"is connected to a negative input terminal, and node"D"is connected to a positive input terminal, respectively, of amplifier 114. Node"D"is also connected to ground through a resistor having a resistance value R8, and an output 148 of amplifier 114 is connected to node"C"via a feedback path 150, which includes a resistor 152 also having a resistance value of R8, respectively, such that the collective amplifiers 110,112 and 114 act to remove the common mode voltage between the respective source and drain terminals 98 and 100 of MOSFET 96, and amplify the remaining differential voltage by a factor of R8/R7 * [1 + 2* (R5/R6)]- The output 148 of amplifier 114 is then applied to the MOSFET gate terminal 106, wherein a selected gate resistor 154 is inserted across the output signal 148 in order to limit the amount of current required to apply the threshold gate voltage, as well as to help prevent ON/OFF oscillations. As can be seen, an advantage of the

alternate MOSFET control circuit of FIG. 4 is that no additional gain stage amplification is required.

While embodiments and applications of this invention have been shown and described, as would be apparent to those skilled in the art, many more modifications and applications are possible without departing from the inventive concepts herein.

The scope of the disclosed inventions, therefore, are not to be restricted except in the spirit of the appended claims.