Description

FLEXIBLE PRINTED CIRCUIT BOARD HAVING FLIP CHIP

BONDING AREA WITH TOP LAYER BUMP AND INNER

LAYER TRACE ALIGNED THEREIN

Technical Field

[1] The present invention relates to a flexible printed circuit board (FPCB), and more particularly, to an FPCB having a flip chip bonding area with a top layer bump and an inner layer trace aligned therein, wherein the top layer bump and the inner layer trace are formed to overlap with each other in the flip chip bonding area so that pattern alignment can be improved and a flip chip process capability can be enhanced. Background Art

[2] In a process of fabricating a semiconductor chip, processes such as etching and deposition are performed on a wafer basis, and then, a test and final packaging are sequentially performed. The packaging refers to a process of mounting a chip on a substrate with an outer lead formed thereon and performing plastic molding. The outer lead (external terminal) is positioned in a bonding area of the substrate and refers to a terminal for electrically connecting the substrate and the chip to each other. According to connection forms of the outer lead and the chip, there are wire bonding, and flip chip bonding.

[3] The wire bonding is a technique inwhich a semiconductor chip is mounted on a substrate with a lead formed thereon and an electrode pattern of the semiconductor chip is connected through a minute wire to an inner lead electrically connected to an outer lead.

[4] Meanwhile, the flip chip bonding is a technique in which a projection such as a solder ball is formed on an electrode pattern or inner lead of a chip so that upon mounting of the chip on a bonding area of a substrate, the projection can be electrically connected to the substrate. Accordingly, with the use of the flip chip bonding, it is possible to reduce a space required for the wire bonding, resulting in fabrication of a small package.

[5] Recently, a flip chip is often bonded on a flip chip bonding area of an FPCB. That is, in the flip chip bonding area of the FPCB, a bump formed on the FPCB and an electrode formed on one surface of the flip chip are electrically connected to each other by means of the flip chip bonding.

[6] Meanwhile, the FPCB may be configured to have a multi-layered structure. In this case, a top layer bump and an inner layer trace are electrically connected to each other. In a general process of fabricating the FPCB, however, the top layer bump and the

inner layer trace are formed without considering alignment relationship therebetween.

[7] However, to achieve a higher degree of space utilization and enhance a flip chip process capability upon fabrication of the FPCB, it is necessary to maintain alignment of the top layer bump and the inner layer trace to a certain extent. Disclosure of Invention Technical Solution

[8] The present invention is conceived to solve the aforementioned problems. Accordingly, an object of the present invention is to provide an FPCB having a flip chip bonding area with a top layer bump and an inner layer trace aligned therein, wherein the top layer bump and the inner layer trace are formed to overlap with each other in the flip chip bonding area so that pattern alignment can be improved, and the width of the inner layer trace is formed to be larger by a certain amount than that of the top layer bump so that a degree of space utilization can be optimized.

[9] According to the present invention for achieving the object, there is provided a flexible printed circuit board having aflip chip bonding area with a top layer bump and an inner layer trace aligned therein, whereinthe top layer bump and the inner layer trace are formed to overlap with each other in the flip chip bonding area, and the width of the inner layer trace is larger than that of the top layer bump. That is, the inner layer trace and the top layer bump are formed to be aligned with each other, wherein the inner layer trace is formed to have a width larger than that of the top layer bump.

[10] Preferably, the width of the inner layer trace is larger by 5 to 20% than that of the top layer bump.

[11] An occupation ratio of copper constituting the trace on an inner layer in the flip chip bonding area may be larger than that of copper constituting the bump on a top layer in the flip chip bonding area.

[12] Further, the relationship between the widths of the inner layer trace and the top layer bump may beapplied to a flexible printed circuit board comprising at least two layers. Brief Description of the Drawings

[13] The above and other objects, features and advantages of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

[14] Fig. 1 is a plan view of a flip chip bonding area of a flexible printed circuit board

(FPCB) according to an embodiment of the present invention

[15] Fig. 2 is a sectional view of the flip chip bonding area of the FPCB according to the embodiment of the present invention

[16] Fig. 3 is a schematic view illustrating an alignment state of a top layer bump and an

inner layer trace in the flip chip bonding area of the FPCB according to the embodiment of the present invention; and

[17] Figs. 4 (a) to (c) are schematic views illustrating respective occupation ratios of a top layer bump and an inner layer trace on top and inner layers in a flip chip bonding area of an FPCB according to an embodiment of the present invention. Mode for the Invention

[18] Hereinafter, preferred embodiments of an FPCB having a flip chip bonding area with a top layer bump and an inner layer trace aligned therein according to the present invention will be described in detail with reference to the accompanying drawings.

[19] Fig. 1 is a plan view of a flip chip bonding area 10 of an FPCB having a flip chip bonding area with a top layer bump and an inner layer trace aligned therein according to an embodiment of the present invention, and Fig. 2 is a sectional view of the flip chip bonding area 10. Further, Fig. 3 is a schematic view illustrating alignment relationship between the top layer bump and the inner layer trace in the flip chip bonding area.

[20] As shown in Figs. 1 and 2, in the flip chip bonding area 10 of the FPCB, the top layer bump 13 positioned at an upper side is represented in blue and the inner layer trace 11 positioned at a lower side is represented in yellow.

[21] The top layer bump 13 and the inner layer trace 11 in the flip chip bonding area 10 are formed to overlap with each other one above another. That is, they are formed not in a random state but in a state where they are aligned to a certain extent while overlapping with each other.

[22] More specifically, the top layer bump 13 and the inner layer trace 11 in the flip chip bonding area 10 are formed to overlap with each other, wherein the width of the inner layer trace 11 is preferably larger than that of the top layer bump 13.

[23] Fig. 3 is a schematic view illustrating an alignment state of the top layer bump 13 and the inner layer trace 11.

[24] As shown in Fig. 3, the top layer bump 13 and the inner layer trace 11 are aligned in a state where they overlap with each other with a PI film 15 interposed therebetween, and it can be seen that the width (denoted by "b" in Fig. 3) of the inner layer trace 11 is formed to be larger than that (denoted by "a" in Fig. 3) of the top layer bump 13.

[25] Preferably, the width of the inner layer trace 11 is formed to be larger by 5 to 20% than that of the top layer bump 13.

[26] For example, if the width of the top layer bump 13 is lOOμm, the width of the inner layer trace 11 may be determined in a range of 105 to 120μm.

[27] It is preferred that in view of improvementof alignment, the inner layer trace 11 be formed to have a width larger than that of the top layer bump 13 while equally

extending at both sides beyond the top layer bump 13.

[28] In the aforementioned FPCB, the degree of alignment is improved so that space utilization can be increased and a flip chip process capability can be enhanced.

[29] Meanwhile, in Fig. 4 (a), there is shown a toplayer in a flip chip bonding area, and a pattern represented in red indicates copper constituting a bump. Further, in Fig. 4 (b), there is shown an inner layer in the flip chip bonding area, and a pattern represented in yellow indicates copper constituting a trace. Furthermore, in Fig. 4 (c), there is shown a state where the top layer and the inner layer are superimposed on each other in the flip chip bonding area.

[30] As shown in Figs. 4 (a) to (c), an occupation ratio of the copper constituting the trace on the inner layer in the flip chip bonding area is larger than that of the copper constituting the bump on the top layer in the flip chip bonding area. That is, assuming that the occupation ratio of the copper constituting the bump on the top layer in the flip chip bonding area is 70%, the occupation ratio of the copper constituting the trace on the inner layer in the flip chip bonding area is 70% or more.

[31] As described above, both the relationships between the widths of the inner layer trace 11 and the toplayer bump 13 and between the occupation ratios of the copper constituting the bump and trace on the top and inner layers may also be applied to an FPCB comprising at least two layers. That is, even in a case where an FPCB comprises multiple layers, the FPCB is preferably fabricated to have the aforementioned structure in order to enhance pattern alignment.

[32] In the FPCBs having the flip chip bonding area with the top layer bump and the inner layer trace aligned thereinaccording to the preferred embodiments of the present invention constructed above, there are advantages in that the top layer bump and the inner layer trace are formed to overlap with each other in the flip chip bonding area so that pattern alignment can be improved, and the width of the inner layer trace is larger by a certain amount than that of the top layer bump so that a degree of space utilization can be optimized and a flip chip process capability can be enhanced.