Title:
IMPEDANCE MATCHING CIRCUIT, IMPEDANCE MATCHING METHOD AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/026918
Kind Code:
A1
Abstract:
The present disclosure provides an impedance matching circuit, an impedance matching method and a semiconductor memory. The circuit comprises a driving module, a calibration module, a digital logic module, a receiving module and a first resistor, wherein an output end of the driving module is connected to the receiving module, and an output end of the calibration module is connected to the first resistor; the calibration module is configured to cooperate with the driving module to perform calibration processing according to the impedance values of the first resistor and the receiving module, and determine a plurality of calibration parameters obtained under different output level values; the digital logic module is configured to receive the plurality of calibration parameters, and determine respective target calibration parameters of at least one transistor group in the driving module; and the driving module is configured to receive the target calibration parameters, and perform impedance adjustment on the at least one transistor group according to the target calibration parameters, such that there is an impedance matching relationship between the impedance value of the driving module and the impedance value of the receiving module under different output level values.
Inventors:
JI YIFAN (CN)
Application Number:
PCT/CN2022/112130
Publication Date:
February 08, 2024
Filing Date:
August 12, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/02
Foreign References:
| CN110289031A | 2019-09-27 | |||
| CN114242129A | 2022-03-25 | |||
| CN110914904A | 2020-03-24 | |||
| CN101256826A | 2008-09-03 | |||
| US20100202227A1 | 2010-08-12 | |||
| US11196418B1 | 2021-12-07 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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