Field of the invention

[0001] The present invention relates to improved circuit integration involving I2C. Particularly, the invention relates to circuit integration for connection between the I2C interface of an application processor and I2C circuitry.

Background art

[0002] State of the art application processors are commonly provided with an I2C interface for connection to one or more I2C slave devices. Given the popularity of such interface, I2C provides a robust and convenient means for processor interfacing. However, any I2C system with multiple devices is also prone to the common limitations of I2C with respect to extendibility. This may relate to problems of parasitic long wires, signal bouncing, signal integrity, EMI susceptibility, IO pin limitations.

[0003] Additionally, I2C is restricted by limited address space, giving rise to issues with duplicate addresses.

[0004] Several approaches have been proposed to tackle these challenges, but only do so partially, thereby suffering from larger footprint and/or larger bill of materials (e.g., owing to discrete implementation) and/or lack of modularity and/or lack of flexibility.

[0005] US20170222829A1 , CN113448402A, and WO2015195329A2 disclose related methods and devices but are overly complex and/or lack flexibility.

[0006] US8832339B1 discloses related systems but lacks modularity.

[0007] The present invention aims at addressing issues, such as the issues mentioned above.

Summary of the invention

[0008] According to a first aspect, the present invention provides a device, preferably an extension module, comprising: an I2C path section for realizing a 4W I2C path toward an application processor and a further device; a local I2C module connected to local I2C circuitry via a two wire, 2W, connection; wherein the I2C path section is provided as four wire, 4W, connection; wherein the local I2C module comprises a static voltage offset means for converting between unidirectional signals carried in opposite directions over two 2W pairs of said 4W path and bidirectional signals carried over said 2W connection toward the local I2C circuitry.

[0009] In embodiments, relating to the system according to the invention, the device is an extension module that provides an extension with respect to a base module comprising said application processor, wherein the base module and extension module are separate modules preferably connectable via a connector. The device may thereby communicate with the application processor, on the one hand, and the further device, on the other hand. In embodiments, at least one of the application processor and the further device does not belong to the device. In preferred embodiments, neither the application processor nor the further device belongs to the device. In related embodiments, the further device is another separate module preferably being a second extension module connectable to the extension module which, in its turn, is connectable to the base module comprising the application processor, the modules preferably being connectable by means of respective connectors.

[0010] In preferred embodiments, the I2C path section provided as 4W connection comprises two respective wires carrying two respective unidirectional signals toward the application processor and two respective wires carrying two respective unidirectional signals away from the application processor. This relates to said unidirectional signals being carried in opposite directions over two 2W pairs.

[0011] In preferred embodiments, said path comprising four wires carries two respective unidirectional signals toward the application processor over two respective wires, and two other respective unidirectional signals away from the application processor over the other respective two wires. This relates to said unidirectional signals being carried in opposite directions over two 2W pairs.

[0012] A variety of advantages of such a device may relate to the modular architecture provided by the 4W unidirectional signal transmission, which may be described as a unidirectional push-pull interface. Thereby, the static voltage offset means enable a transparent conversion between the 2W bidirectional signals of the processor and the local I2C circuitry, on the one hand, and the 4W unidirectional signal transmission in-between. It may advantageously allow to bridge the distances between devices and processor while maintaining signal integrity. As may be understood by the skilled person, maintaining signal integrity over traditional 2W I2C connections requires complex hardware, whereas 4W unidirectional signals may suffer less EMI susceptibility and, crucially, may be "cleaned up" at the level of each device by means of simple unidirectional signal repeaters, allowing to operate in environments that are more challenging and/or more electronically "dirty", relating to larger distances and/or more EMI. Thereby, communication between the application processor, the device, and a certain number of further devices may be possible over increased distance. The architecture thereby affords to choose the number of further devices according to user requirements, enabling modularity.

[0013] Related, the transparent conversion between the 2W bidirectional signals and the 4W unidirectional signals conveniently enables that the application processor may have the local I2C circuitry at the device(s) available as if they were attached directly to the processor's 2W I2C interface. This, in turn, may allow that the OS of the processor uses the device drivers supplied by the manufacturer of the local I2 circuitry (e.g., one or more slave devices), without any need for customisation of these drivers or extra middleware, and hence, without the risk of seeing system performance reduced owing to such customized drivers or middleware. This transparency may be enabled by the advantageous conversion, by the static voltage offset means, between 2W bidirectional signals a 4W unidirectional signals.

[0014] Furthermore, the invention may advantageously mitigate the problems of parasitic long wires, signal bouncing, signal integrity, EMI susceptibility, and IO pin limitations. [0015] Such advantages are not provided by the system described in US8832339B1 , which merely relates to interfaces on a first device that are configured such that a first synchronous interface is set to a slave mode while a second synchronous interface is set to a master mode.

[0016] In embodiments, issues with duplicate addresses may be overcome through address translation.

[0017] According to a second aspect, the invention provides a system comprising: a base module comprising:

■ an application processor comprising a two wire, 2W, I2C interface;

■ second static voltage offset means for converting between bidirectional signals of said 2W I2C interface of the application processor and 4W unidirectional signals carried in opposite directions over two 2W pairs of a 4W I2C path; one or more devices, each device comprising:

■ a 4W I2C path section for realizing said 4W I2C path toward the 4W unidirectional signals originating from the application processor and another one of the one or more devices;

■ a local I2C module connected to local I2C circuitry via a two wire, 2W, connection, comprising a static voltage offset means for converting between the 4W unidirectional signals carried in opposite directions over two 2W pairs of said 4W path and bidirectional signals carried over said 2W connection toward the local I2C circuitry.

[0018] The system may provide the advantages of the device comprised in it. Moreover, it may provide additional advantages relating the base module. Particularly, the base module may be produced at reduced cost in view of not requiring application specific components such as specific I2C bus extenders, such as prior art approaches converting the single-ended I2C bus to a different type of signal type (e.g., PCA9615, or I2C to LVDS, or analog device's A2B) or very specific implementations (e.g., those based on LVDS technology using a dedicated FPGA translating register mapped IO and digital audio to an LVDS bus). Instead, the second static voltage offset means may relate to a simple, inexpensive pair of transistors. Also, for the base module the extension interface pin count may be kept low. This relates at least to the I2C interface that is guided via the path, preferably at least for control-related I2C signals, and, in embodiments, may also relate to using buses for IO and/or audio (TDM). Furthermore, by enabling using native processor interfaces (I2C, optionally also TDM, ...) and thereby using them as intended (e.g., attaching I2C IO extenders to it using the standard device drivers) the software development may be reduced and/or robust and fast operation may be attained. This may be contrasted with prior art devices which require specific implementation in the processor.

[0019] According to a further aspect, the invention provides a method for configuring a system comprising a base module and one or more devices each comprising a configurable module and a self-configuration engine; the method comprising the steps of: providing, to each of the devices, different respective configuration instructions for storage on a respective EEPROM module comprised in the respective device, connecting a 4W path section of the first device to the base module, and each 4W path section of the respective further device to the 4W path section of the respective previous device, so that a 4W I2C path is realized toward an application processor comprised in the base module; said path relating to second static voltage offset means comprised in the base module that convert between 4W unidirectional signals carried in opposite directions over two 2W pairs of the 4W I2C path and bidirectional signals of an 2W I2C interface of the application processor; have the self-configuration engine, based upon a trigger for self-configuration, carry out the steps of:

■ loading the configuration instructions from the EEPROM module; and

■ configuring, based on the instructions, the configurable module, the configurable module preferably relating to one or more of: an address translation module, a TDM multiplexer module, an I2C IO extender, an SPI chip select module, a DART chip select module.

[0020] Such a method may have advantages similar to the device and the system according to the invention.

[0021] Preferred embodiments and their advantages are provided in the description and the dependent claims.

Brief description of the drawings

[0022] The present invention will be discussed in more detail below, with reference to the attached drawings.

[0023] Figure 1 shows a first example device as part of a first example system according to the invention.

[0024] Figure 2 shows a second example device according to the invention.

[0025] Figure 3 shows a third example device as part of a third example system according to the invention.

[0026] Figure 4 shows various example embodiments of the device of the invention.

Description of embodiments

[0027] The following descriptions depict only example embodiments and are not considered limiting in scope. Any reference herein to the disclosure is not intended to restrict or limit the disclosure to exact features of any one or more of the exemplary embodiments disclosed in the present specification.

[0028] Furthermore, the terms first, second, third and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. The terms are interchangeable under appropriate circumstances and the embodiments of the invention can operate in other sequences than described or illustrated herein. [0029] Furthermore, the various embodiments, although referred to as “preferred” are to be construed as exemplary manners in which the invention may be implemented rather than as limiting the scope of the invention.

[0030] The term “comprising”, used in the claims, should not be interpreted as being restricted to the elements or steps listed thereafter; it does not exclude other elements or steps. It needs to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising A and B” should not be limited to devices consisting only of components A and B, rather with respect to the present invention, the only enumerated components of the device are A and B, and further the claim should be interpreted as including equivalents of those components.

[0031] In this document, the term "extension module" refers to the device of the invention, whereby the term "extension" should not be construed as limiting the device in any way, and refers to one possible use of the device, connecting it to a base module. However, it should be noted that in some embodiments the application processor of the invention may also reside within the device, without any base module being present, illustrating that the term "extension" should not be construed as limiting. Likewise, the term "extension" may also refer to the address space extension enabled through the address translation module, although both embodiments of the device with and without address translation module fall within the scope of the invention.

[0032] In this document, reference is made to 4W signals carrying data originating from 2W I2C interfaces. In (PCA9615 Product data sheet, 2-channel multipoint Fast-mode Plus differential I2C- bus buffer with hot-swap logic, Rev. 2 - 16 September 2021 , see, e.g., https://www.nxp.com/docs/en/data-sheet/PCA9615.pdf, hereafter PCA9615) there is also mention of "4W I2C", but not in any way compatible with the invention. Particularly, (PCA9615) does not disclose unidirectional signals but instead teaches two differential bidirectional pairs. This relates to the different aim of (PCA9615), directed at a multi-drop setup, teaching away from any form of I2C distribution means. In contrast, according to embodiments, the invention enables point-to- (repeated)-point with a T- connection.

[0033] In the context of the invention, static voltage offset may, e.g., relate to using two levels for the active state (for I2C the active state is low (~0V), since open drain outputs are used) on the I2C line, namely 'low of the I2C slave (e.g., 0V)' and 'low of the path (e.g., 0.5V)'. High may relate to a higher voltage level, e.g., 3.3V. Thereby, a comparator may detect the direction of the signal (driver of the active signal is the path or driver is the slave). Through the comparator, the direction may be known, and a lock-up condition may be prevented.

[0034] In this document, reference is made to static voltage offset means as a means for conversion between 2W and 4W. In (F. Houde; Why, When, and How to use I2C Buffers, Tl Application report SCPA054 - July 2018, see, e.g., https://www.ti.com/lit/an/scpa054/scpa054.pdf, hereafter SCPA054) it is explained how an I2C buffer may benefit from static voltage offset. This said, (SCPA054) cannot disclose or suggest the invention, since it is directed merely at local buffering, and does not relate to providing transparency on a path toward an application processor, a device, and a further device.

[0035] In this document, "daisy chain topology" refers to the concatenation of two or more building blocks according to a repeating pattern. This may, e.g., relate to a base module connected to a device, which, in its turn, is connected to one or more further devices. In case of a single device and a single base module, there is no repeating pattern, and the topology relates to a mere path between the device and the base module. [0036] The application processor may be any processor comprising an I2C interface, preferably a 2W I2C interface. In examples, the application processor is an i.MX 6 series processor with ARM 9 or ARM 7, yet any l2C-enabled application processor may be considered. Thereby, the I2C interface preferably allows to connect to a variety of slave devices, such as: memory, IO expanders, displays, sensors, ADCs, DACs, a GNSS such as GPS.

[0037] The advantages of the invention, in its various embodiments, may relate to overcoming one or more of the common limitations of: parasitic long wires, repeated addresses, signal bounce, signal integrity, IO pin limitations, and EMI susceptibility. Prior art approaches use discrete components that each solve a single limitation, but do not combine those in an integrated fashion, as is the case for the invention. For instance, in prior art devices, 4W I2C may allow longer lines through signal regeneration/repeating, which would be very difficult with 2W I2C, but is never proposed with a path according to the invention, connecting the application processor, a device, and a further device, wherein the path realizes a 4W "backbone". In other prior art examples, address translators enable address duplication, but are merely proposed for translation directly at the I2C interface of the processor. In other prior art examples, debouncers are provided yet are operating only at a local connection level, and not at system level. In other prior art examples, GPIO extenders allow for IO extension beyond the GPIO pins but are proposed merely at the application processor. Additionally, each of these discrete components add to the complexity of the design and to the bill of materials. The invention overcomes these drawbacks by means of an integrated solution with respect to I2C distribution. In embodiments, the invention enables an in - out principle per device (or extension module), allowing signals to be repeated or switched per device. This may facilitate achieving good signal integrity, whereby signals get cleaned up on each device, yielding reliable I2C distribution. In embodiments, the use of an FPGA combined with 4W I2C advantageously overcomes several physical limitations of the standard 2W I2C bus (e.g., addressing, capacitive load, EMI susceptibility).

[0038] In embodiments, the same FPGA may thereby be used to enable a highly compressed audio interface native to the CPU (16-channel TDM). Such an interface is often not supported by the electronics on the extension boards. In embodiments, the FPGA may perform the signal translation from 16-channel TDM to the commonly supported I2S through a simple programmable TDM multiplexer module. This module may, e.g., simply select the correct time slot. The distribution may be transparent to the processor, and even more so in embodiments relying on an FPGA. Transparency may thereby enable the reuse of default drivers.

[0039] In embodiments, the I2C path section is configured for realizing said 4W I2C path according to a daisy chain topology wherein the path extends between the application processor and the device, on the one hand, and between the device and the further device, on the other hand.

[0040] In embodiments, the device further comprises: an I2C repeater module for unidirectional repeating of said unidirectional signals carried over said path being a 4W I2C path, preferably relating to respective submodules for: master in slave out (MISO) serial data (SDA); master out slave in (MOSI) SDA; master out slave in (MISO) serial clock (SCL); and MOSI SCL. [0041] In embodiments, the device further comprises: an address translation module for providing address translation between a global address over said path and a local I2C address for the local I2C circuitry.

[0042] In embodiments, the address translation module is a 4W module connected to the I2C path section and the local I2C module.

[0043] In embodiments, the device further comprises: an EEPROM module, preferably an I2C EEPROM module, comprising configuration instructions; a self-configuration engine; a configurable module; wherein the self-configuration engine is configured to, upon a trigger for self-configuration, carry out the steps of: loading the configuration instructions from the EEPROM module; and configuring, based on the instructions, the configurable module, the configurable module preferably relating to one or more of: an address translation module, a TDM multiplexer module, an I2C IO extender, an SPI chip select module, a DART chip select module.

[0044] In embodiments, the device further comprises: a TDM multiplexer module; respective audio interfaces for connecting the TDM multiplexer module toward the application processor and the further device; an audio codec module, preferably an I2S audio codec module, connected to said TDM multiplexer module; wherein the TDM multiplexer module is configured for routing audio data between the audio interfaces and the audio codec module over a TDM time slot dedicated to said device, wherein preferably said TDM time slot is dedicated based on configuration instructions stored in an I2C EEPROM module comprised in the device.

[0045] In embodiments, the device further comprises: an I2C IO extender; user I2C IO circuitry connected to said IO extender; wherein said IO extender comprises an IO extender output and an IO extender input, preferably an IO extender input comprising a debouncer; wherein said IO extender is a 4W IO extender connected to said I2C path section via the address translation module for providing address translation between a global address over said path and the local I2C address for the user I2C IO circuitry. In related embodiments, the I2C IO extender is not a 4W but a 2W IO extender. In such embodiments, the 2W IO extender may, e.g., belong to the local I2C circuitry and interface with the address translation module and the I2C path section via the local I2C module.

[0046] In embodiments, the device further comprises: an SPI chip select module; an SPI multiplexer module connected to the SPI chip select module; local SPI circuitry connected to said SPI multiplexer module; respective SPI interfaces for connecting the SPI multiplexer module toward the application processor and the further device; wherein the SPI multiplexer module is configured for routing SPI data between an SPI interface and either the other SPI interface or the SPI local circuitry based on a switching determined by the SPI chip select module, wherein preferably said switching is based on configuration instructions stored on an EEPROM module comprised in the device.

[0047] In embodiments, the device further comprises: a DART chip select module; a DART multiplexer module connected to the DART chip select module; local DART circuitry connected to said DART multiplexer module; respective DART interfaces for connecting the DART multiplexer module toward the application processor and the further device; wherein the DART multiplexer module is configured for routing DART data between a DART interface and either the other DART interface or the UART local circuitry based on a switching determined by the UART chip select module, wherein preferably said switching is based on configuration instructions stored on an EEPROM module comprised in the device.

[0048] In embodiments, at least said I2C path section and said I2C repeater module are comprised in a same FPGA belonging to the device, wherein preferably the same FPGA further comprises one or one or more of, more preferably comprises each of: an address translation module, a TDM multiplexer module, an I2C IO extender, an SPI chip select module, a UART chip select module, a self-configuration engine. Such embodiments may advantageously provide ease of implementation of a variety of functions, afforded by the FPGA. In embodiments, this includes the implementation of the self-configuration engine 209. This functionality makes it possible to reuse the complete FPGA design without any alteration on the different devices (e.g., extension modules). In examples, multiple devices with the exact same hardware may be attached to the application module (e.g., base module), only requiring changing the respective configuration instructions stored on the respective EEPROM modules. The storing of configuration instructions may be performed, e.g., during device production. Moreover, owing to the transparency of the path, local I2C circuitry, e.g., attached slave devices, may be available to the application processor as if they were attached directly to the processor's peripheral interfaces themselves.

[0049] In embodiments, the addition of a further device, e.g., an extension module, is selfconfiguring. This may relate to the base unit detecting extension modules by itself and configuring itself to use them. To this end, an EEPROM present on the I2C circuitry on every extension module may define the type of extension module. This may create a problem with I2C addresses as EEPROM I2C addresses are very limited (an industry standard range of a small number, e.g., 8, addresses is used for I2C EEPROM's). Such a low number may mean that only this number of different extension modules could be designed. This may advantageously be overcome by the I2C address translation. Thereby, also the address translation mask may be defined in the EEPROM. This mask may be configured during production, making it possible to use twice the same extension module in hardware, attached to one base unit. At power on the FPGA may read out the address mask and then translate all local I2C addresses accordingly. This may allow that two of the same extension modules (hardware) configured with a different address mask show up as different extension modules to the base unit.

[0050] In embodiments, apart from the EEPROM, other I2C devices use the address translation, making it possible to reuse the same components (with the same addresses, e.g., I2C configurable audio codecs, I2C temperature sensors) on different extension modules. This may relate to said self-configuring.

[0051] In embodiments, TDM channel selection is also configured in the EEPROM. Preferably this is programmed with corresponding configuration instructions during production. This may tell the base unit which TDM audio slots the specific extension module uses (e.g., an extension module with 4 power amplifiers can be configured to use slots 1-4 (of the 16), the next extension module with, e.g., 2 microphones may be configured to use slots 5 & 6, the same extension module with another 2 mic inputs may be configured to use 7 & 8). The TDM slots may be demultiplexed (for DAC) and multiplexed (for ADC) on the extension board enabling to use codec devices using the standard 2-channel I2S digital audio protocol, which is widely supported.

[0052] In embodiments with an FPGA, the FPGA comprises said I2C repeater module consisting of respective submodules for MISO SDA, MOSI SDA, MISO SCL, and MOSI SCL. This may advantageously provide a reliable means of signal integrity maintenance that may be straightforward to implement.

[0053] In embodiments, the system comprises at least two respective devices each comprising a respective same configurable module each configured through respective configuration instructions stored in respective I2C EEPROM modules comprised in the respective device.

[0054] In embodiments relating to the system, said configuration relates to a respective selfconfiguration engine comprised in the respective device and configured to, upon a trigger for selfconfiguration, carry out the steps of: loading the configuration instructions from the respective I2C EEPROM module; and configuring, based on the instructions, the respective configurable module. Thereby, the trigger may preferably relate to, e.g., power on.

[0055] In embodiments, signals not relating to bus signals or I2C signals are also present on the interface of the device. This may relate, e.g., to one or more of:

■ ETH: if used a switch may be provided in the device to make a Y-connection.

■ USB: is used for programming the device in production via the easily reachable extension interface (not needed to screw open the device, unmount boards etc), if used for other purposes (e.g. a USB disk-on-module), whereby a local USB hub may be provided in the device to make a Y-connection.

■ UART: may be used for debug purposes with easy access. In embodiments, e.g., with other or additional purposes, (e.g., RS485 connection), an UART multiplexer may be provided in the device to make a Y-connection.

[0056] In embodiments, redundant power is available through the extension interface. This makes it possible to power the extension modules from the base unit (redundantly: with 2 PSU's in the base unit) or to power the base unit with a specific PSU extension modules or a combination of both.

[0057] In embodiments, the application processor comprises a peripheral audio interface, preferably an I2S interface, comprising a plurality of multiplexed audio channels, and the respective data processing means at the extension module are implemented with respective FPGAs comprising a multiplexer/demultiplexer for adding/extracting at least one respective audio channel to/from the plurality of multiplexed audio channels. This may advantageously provide for integration of l2C-based functionality and audio functionality with the same (FPGA) hardware. In preferred embodiments, the number of multiplexed audio channels, e.g., TDM audio channels, is at least 8 or 16 channels, with at least one channel for input and one for output with respect to at least one extension module.

[0058] According to further aspects, which are not limiting the scope in any way, the invention relates to following clauses 1-15:

[0059] Clause 1 . A device (2) comprising: an I2C path section for realizing a path (72) toward an application processor (10) and a further device (3); a local I2C module (204) connected to local I2C circuitry (30, 74) via a two wire, 2W, connection; wherein the I2C path section is provided as four wire, 4W, connection; wherein the local I2C module (204) comprises a static voltage offset means (73) for converting between unidirectional signals carried over said path (72) and bidirectional signals carried over said 2W connection toward the local I2C circuitry (30, 74).

[0060] Clause 2. Device (2) of clause 1 , further comprising: an I2C repeater module (120a, 120b) for unidirectional repeating of said unidirectional signals carried over said path (72) being a 4W I2C path, preferably relating to respective submodules for: master in slave out, MISO, serial data, SDA; master out slave in, MOSI, SDA; master out slave in, MISO, serial clock, SCL; and MOSI SCL.

[0061] Clause 3. Device (2) of clause 1 or 2, further comprising: an address translation module (203) for providing address translation between a global address over said path (72) and a local I2C address for the local I2C circuitry (30, 74).

[0062] Clause 4. Device (2) of clause 3, wherein the address translation module (203) is a 4W module connected to the I2C path section and the local I2C module (204).

[0063] Clause 5. Device (2) of any of clauses 3-4, further comprising: an I2C IO extender (202); user I2C IO circuitry (26) connected to said IO extender; wherein said IO extender comprises an IO extender output (260) and an IO extender input (270), preferably an IO extender input comprising a debouncer; wherein said IO extender is a 4W IO extender connected to said I2C path section via the address translation module (203) for providing address translation between a global address over said path (72) and the local I2C address for the user I2C IO circuitry (26).

[0064] Clause 6. Device (2) of any of clauses 1-5, further comprising: an EEPROM module (302), preferably an I2C EEPROM module, comprising configuration instructions; a self-configuration engine (209); a configurable module (203, 208, 202, 205, 206); wherein the self-configuration engine (209) is configured to, upon a trigger for selfconfiguration, carry out the steps of: loading the configuration instructions from the EEPROM module; and configuring, based on the instructions, the configurable module, the configurable module preferably relating to one or more of: an address translation module (203), a TDM multiplexer module (208), an I2C IO extender (202), an SPI chip select module (205), a DART chip select module (206).

[0065] Clause 7. Device (2) of any of clauses 1-6, further comprising: a TDM multiplexer module (208); respective audio interfaces (140, 140') for connecting the TDM multiplexer module toward the application processor (10) and the further device (3); an audio codec module (23, 24), preferably an I2S audio codec module, connected to said TDM multiplexer module; wherein the TDM multiplexer module is configured for routing audio data between the audio interfaces (140, 140') and the audio codec module (23, 24) over a TDM time slot dedicated to said device (2), wherein preferably said TDM time slot is dedicated based on configuration instructions stored in an I2C EEPROM module (302) comprised in the device.

[0066] Clause 8. Device (2) of any of clauses 1-7, further comprising: an SPI chip select module (205); an SPI multiplexer module (201 ) connected to the SPI chip select module (205); local SPI circuitry (25) connected to said SPI multiplexer module (201 ); respective SPI interfaces (140, 140') for connecting the SPI multiplexer module toward the application processor (10) and the further device (3); wherein the SPI multiplexer module (201 ) is configured for routing SPI data between an SPI interface (140) and either the other SPI interface (140') or the SPI local circuitry (25) based on a switching determined by the SPI chip select module (205), wherein preferably said switching is based on configuration instructions stored on an EEPROM module (302) comprised in the device.

[0067] Clause 9. Device (2) of any of clauses 1-8, further comprising: a DART chip select module (206); a DART multiplexer module (207) connected to the DART chip select module (206); local DART circuitry (22) connected to said DART multiplexer module (207); respective DART interfaces (130, 130') for connecting the DART multiplexer module toward the application processor (10) and the further device (3); wherein the DART multiplexer module (207) is configured for routing DART data between a DART interface (130) and either the other DART interface (130') or the DART local circuitry (22) based on a switching determined by the UART chip select module (206), wherein preferably said switching is based on configuration instructions stored on an EEPROM module (302) comprised in the device.

[0068] Clause 10. Device (2) of any of clauses 2-9, wherein at least said I2C path section and said I2C repeater module (120a, 120b) are comprised in a same FPGA (21 ) belonging to the device, wherein preferably the same FPGA further comprises one or one or more of, more preferably comprises each of: an address translation module (203), a TDM multiplexer module (208), an I2C IO extender (202), an SPI chip select module (205), a UART chip select module (206), a selfconfiguration engine (209).

[0069] [0070] Clause 11. Device (2) of clause 10, wherein said I2C repeater module (120a, 120b) belonging to the FPGA (21 ) consists of respective submodules for MISO SDA, MOSI SDA, MISO SCL, and MOSI SCL.

[0071] Clause 12. A system comprising: a base module (1 ) comprising:

■ an application processor (10) comprising a two wire, 2W, I2C interface (12);

■ second static voltage offset means (16, 71 ) for converting between bidirectional signals of said 2W I2C interface (12) of the application processor (10) and 4W unidirectional signals; one or more devices (2, 3), preferably each device being according to any of clauses 1-10, each device comprising:

■ a 4W I2C path section for realizing a path (72) toward the 4W unidirectional signals originating from the application processor (10) and another one of the one or more devices (3);

■ a local I2C module (204) connected to local I2C circuitry (30, 74) via a two wire, 2W, connection, comprising a static voltage offset means (73) for converting between the 4W unidirectional signals carried over said path (72) and bidirectional signals carried over said 2W connection toward the local I2C circuitry (30, 74).

[0072] Clause 13. System of clause 12, comprising at least two respective devices each comprising a respective same configurable module (203, 208, 202, 205, 206) each configured through respective configuration instructions stored in respective I2C EEPROM modules (302a, 302b) comprised in the respective device.

[0073] Clause 14. System of clause 13, wherein said configuration relates to a respective selfconfiguration engine (209) comprised in the respective device and configured to, upon a trigger for self-configuration, carry out the steps of: loading the configuration instructions from the respective I2C EEPROM module (302a, 302b); and configuring, based on the instructions, the respective configurable module.

[0074] Clause 15. Method for configuring a system comprising a base module (1 ) and one or more devices (2, 3) each comprising a configurable module (203, 208, 202, 205, 206) and a selfconfiguration engine (209); preferably the system of any of clauses 12-14, the method comprising the steps of: providing, to each of the devices (2, 3), different respective configuration instructions for storage on a respective EEPROM module (302a, 302b) comprised in the respective device (2,3), connecting a 4W path section of the first device (2) to the base module (1 ), and each 4W path section of the respective further device (3) to the 4W path section of the respective previous device (2), so that a path (72) is realized toward an application processor (10) comprised in the base module (1 ); said path relating to second static voltage offset means (16, 71 ) comprised in the base module (1 ) that convert between 4W unidirectional signals of the path and bidirectional signals of an 2W I2C interface (12) of the application processor (10); have the self-configuration engine (209), based upon a trigger for self-configuration, carry out the steps of:

■ loading the configuration instructions from the EEPROM module; and

■ configuring, based on the instructions, the configurable module, the configurable module preferably relating to one or more of: an address translation module (203), a TDM multiplexer module (208), an I2C IO extender (202), an SPI chip select module (205), a DART chip select module (206).

[0075] Example embodiments of the invention will be described with reference to Figs. 1-4.

[0076] Example 1 : first example device and system according to the invention

[0077] This example relates to Figure 1 , showing a first example device being an extension module 2 as part of a first example system according to the invention. As shown, the system further comprises a further example device being a further extension module 3, and a base module 1 comprising the application processor 10. In view of similarities with Example 2-4, merely for the sake of clarity, reference numerals are included in this Example which occur on at least one of Figure 2-4 and not on Figure 1. These reference numerals are however not to be construed as limiting the invention.

[0078] The extension module 2 comprises an I2C path section for realizing a path toward the application processor 10 and the further extension module 3. The path thereby extends between the base module 1 and a program and debug interface 5. Particularly, it extends from the base module 1 toward the extension module 2, and then from the extension module 2 toward the second extension module 3, via respective connectors 4. As shown (suggested by three dots), one or more further extension modules (not shown) may be connected likewise. At the end of the path is said program and debug interface 5, comprising a program interface 51 and a DART debug interface 53 for connecting via a connector. The program and debug interface 5 is configured to be attached to the extension module at the end of the path extending from the base module, or directly to the base module. Furthermore, the program and debug interface is connected to a user interface device 6 such as a PC, allowing to program and debug the system, particularly, program the processor 10 and communicate with it via a RS232 debug interface.

[0079] As illustrated by arrows indicating direction, with each depicted line representing two wires, the path comprises four wires. The path carries two respective unidirectional signals toward the application processor, over two respective wires (one depicted line, arrow pointing toward application processor). Furthermore, the path carries two other respective unidirectional signals away from the application processor, over the other respective two wires (the other depicted line, arrow pointing away from application processor).

[0080] The base module 1 comprises, apart from the application processor running some OS (e.g., Linux OS), a plurality of peripheral interfaces 11 , 12, 13, 14, 15. The peripheral interfaces are, amongst others, for communicating with other IC’s (I2C, SPI), small functional modules (SPI, DART) and audio devices (serial digital audio). Next to the on-board devices and user IO in the base module, the processor interfaces with the extension modules 2, 3. [0081] Particularly, the base module comprises a program interface 11 of the processor, an I2C peripheral interface 12 of the processor, a UART peripheral interface 13 of the processor, a serial digital audio peripheral interface 14 of the processor, and an SPI peripheral interface 15 of the processor.

[0082] The program interface 1 1 of the processor relates to USB and connects, via the extension modules and the connectors, to the program interface 51 of the program and debug interface 5.

[0083] The I2C peripheral interface 12 of the processor is a 2W I2C interface. It connects to said path, whereto a variety of slave devices can be attached (e.g., memory, IO expanders, displays, sensors, ADCs, DACs, a GNSS such as GPS). To communicate with these slave devices, the OS of the processor uses device drivers which may be supplied by the manufacturer of the slave device, without any driver modification being required, owing to the transparency enabled by the path realized according to the invention. To connect to said path, the I2C peripheral interface connects to a second static voltage offset means 16. This relates to a basic discrete conversion between the bidirectional open collector signals of the processor, provided at the I2C peripheral interface 12, and the 4W unidirectional signals 1200, 1200' carried over the path. Particularly, the static voltage offset means thereby converts between unidirectional signals carried in opposite directions over two 2W pairs of the 4W path, on the one hand, and bidirectional signals carried over the 2W connection toward the local I2C circuitry 30. Thereby, the two bidirectional signals relate to a data line and a clock line, driven by open collector outputs. On the other hand, the 4W unidirectional signal transmission may be described as a unidirectional push-pull interface for bridging longer distances while maintaining signal integrity, thereby enabling communication with the extension modules. For the path, only 1 signal is depicted (clock or data).

[0084] The UART peripheral interface 13 of the processor is a point-to-point interface that may be used to communicate with a variety of other devices or modules (e.g., GPS transceiver, RS232 interface transceiver, RS485 bus transceiver). It may also be used to communicate with a console to output debug information. When interfacing with third party devices or modules, drivers suitable for the OS, e.g., Linux OS, may conveniently be available from the provider.

[0085] The serial digital audio peripheral interface 14 of the processor may be set up according to different protocols (e.g., I2S, Left Justified (LJ), TDM). In this example, the interface is set up to 16- channel TDM providing interface possibilities with 16 digital audio inputs and 16 digital audio outputs. It comprises clock signals and data in- and output signals.

[0086] The SPI peripheral interface 15 of the processor relates to a bus whereto a variety of slave devices can be attached (e.g., memory, IO expanders, displays). To communicate with these devices, the OS, e.g., Linux OS, uses device drivers which may be conveniently supplied by the manufacturer of the slave device, without requiring any modification. The bus relates to a clock signal, data in- and output signals and a chip select line for each slave device connected on the bus. In examples, SPI peripheral interface is used for high bandwidth applications, as throughput may be higher than over the I2C interface 12.

[0087] Signals of the processor's program interface 11 , I2C peripheral interface 12, UART peripheral interface 13, serial digital audio peripheral interface 14, and SPI peripheral interface 15 are carried between the application processor 10 and the extension modules 2 via connector 4, the first device on the path being the first extension module 2.

[0088] The first extension module 2 contains extra IO I functionality to attach to a base module. It is built around an FPGA 21 comprised in the extension module interfacing with the processor of the base module, on-board devices, user IO comprised in the extension module, and on-board devices and user IO comprised in the other extension modules.

[0089] The second extension module 3 may have the same hardware as the first or other to add different functionality. Additional extension modules can be connected in the same way, building a whole stack of modules. Thereby, different connectors 4 connect the base module and the first extension module to each other, the first to the next and so on, in a point-to point fashion. This connection is impedance-matched to optimise signal integrity.

[0090] Apart from said extra IO I functionality comprised in the extension module 2 to attach to the base module 1 , the extension module and the second extension module may be essentially the same in terms of hardware. Software-wise, a difference lies in the instructions stored on the I2C EEPROM module 302a, 302a, allowing to dynamically configure the system, by means of the respective self-configuration engines 209a, 209b. Other respective extension modules (not shown) may also be present, which may also be essentially the same. The extension modules 2, 3 each have a respective local I2C module 204 connected to local I2C circuitry 30, 74 via a two wire, 2W, connection. Opposed to this, the respective I2C path sections are provided as four wire, 4W, connection. The local I2C modules 204 comprise a respective static voltage offset means 73 for converting between unidirectional signals carried over said path and bidirectional signals carried over said 2W connection toward the local I2C circuitry 30, 74.

[0091] The extension modules 2, 3 each have an I2C repeater module (not shown; shown on Fig. 2 120a, 120b) for unidirectional repeating of said unidirectional signals carried over said path being a 4W I2C path. This relates to respective submodules for MISO SDA; MOSI SDA; MISO SCL; and MOSI SCL.

[0092] The extension modules 2, 3 each comprise an address translation module 203 for providing address translation between a global address over said path 72 and a local I2C address for the local I2C circuitry 30, 74. Thereby, the address translation module 203 is a 4W module connected to the I2C path section and the local I2C module 204.

[0093] The extension modules 2, 3 each comprise an EEPROM module 302, being an I2C EEPROM module, comprising configuration instructions, as well as a self-configuration engine 209; and a plurality of modules that can be configured, in this example an address translation module 203, a TDM multiplexer module 208, an I2C IO extender 202, an SPI chip select module 205, a DART chip select module 206. The self-configuration engine 209 is configured to, upon a trigger for self-configuration, carry out the steps of: loading the configuration instructions from the EEPROM module; and configuring, based on the instructions, the configurable module, one of the configurable modules.

[0094] The extension modules 2, 3 each comprise a TDM multiplexer module 208; respective audio interfaces 140, 140' for connecting the TDM multiplexer module toward the application processor 10 and the further device 3; and an audio codec module 23, 24, particularly an I2S audio codec module, connected to said TDM multiplexer module. The TDM multiplexer module is configured for routing audio data between the audio interfaces 140, 140' and the audio codec module 23, 24 over a TDM time slot dedicated to said device 2, wherein preferably said TDM time slot is dedicated based on configuration instructions stored in an I2C EEPROM module 302 comprised in the device.

[0095] The extension modules 2, 3 each comprise an I2C IO extender 202; and user I2C IO circuitry 26 connected to said IO extender. Said IO extender comprises an IO extender output 260 and an IO extender input 270. The IO extender input comprises a debouncer. The IO extender is a 4W IO extender connected to said I2C path section via the address translation module 203. It provides address translation between a global address over said path and the local I2C address for the user I2C IO circuitry 26. In other examples (not shown), the I2C IO extender is not a 4W but a 2W IO extender belonging to the local I2C circuitry 30, 74 and interfacing with the address translation module 203 and the I2C path section via the local I2C module 204.

[0096] The extension modules 2, 3 each comprise an SPI chip select module 205; an SPI multiplexer module 201 connected to the SPI chip select module 205; local SPI circuitry 25 connected to said SPI multiplexer module 201 ; and respective SPI interfaces 140, 140' for connecting the SPI multiplexer module toward the application processor 10 and the further device 3. The SPI multiplexer module 201 is configured for routing SPI data between an SPI interface 140 and either the other SPI interface 140' or the SPI local circuitry 25. The routing of SPI data is based on a switching determined by the SPI chip select module 205, particularly on configuration instructions stored on an EEPROM module 302 comprised in the device.

[0097] The extension modules 2, 3 each comprise a DART chip select module 206; a DART multiplexer module 207 connected to the DART chip select module 206; local DART circuitry 22 connected to said DART multiplexer module 207; and respective DART interfaces 130, 130' for connecting the DART multiplexer module toward the application processor 10 and the further device 3. The DART multiplexer module 207 is configured for routing DART data between a DART interface 130 and either the other DART interface 130' or the DART local circuitry 22 based on a switching determined by the DART chip select module 206, particularly on configuration instructions stored on an EEPROM module 302 comprised in the device.

[0098] The extension modules 2, 3 each comprise an FPGA 21 that implements portions of the I2C path section and said I2C repeater module 120a, 120b. The same FPGA further comprises an address translation module 203, a TDM multiplexer module 208, an I2C IO extender 202, an SPI chip select module 205, a DART chip select module 206, a self-configuration engine 209. Thereby, said I2C repeater module 120a, 120b belonging to the FPGA 21 consists of respective submodules for MISO SDA, MOSI SDA, MISO SCL, and MOSI SCL. The modules 203, 208, 202, 205, 206 are configurable modules that are configured through respective configuration instructions stored in respective I2C EEPROM modules 302a, 302b comprised in the respective device. The configuration relates to a respective self-configuration engine 209 comprised in the respective device and configured to, upon a trigger for self-configuration, carry out the steps of: loading the configuration instructions from the respective I2C EEPROM module 302a, 302b; and configuring, based on the instructions, the respective configurable module. This relates to the ease of implementation of a variety of functions afforded by the FPGA, including the implementation of the self-configuration engine 209. This allows for a method wherein the entire system, including the base module 1 and the extension modules 2, 3, are configured at once. This configuration may start, e.g., at production of the modules, by storing adequate configuration instructions on the respective EEPROM module 302a, 302b of the respective extension modules 2,3. Either before but preferably after connecting the base module and the extension modules, the self-configuration engine 209 may receive a trigger for self-configuration, e.g., a power on; a hardware-based trigger (such as pushing a button provided on the device); or a software-based trigger (such as a signal from the EEPROM programming connector 301 or the application processor 10). Upon triggering, the self-configuration engine 209 may load the configuration instructions from the EEPROM module; and configure, based on the instructions, at least the address translation module 203, and additionally also the TDM multiplexer module 208 and/or the I2C IO extender 202 and/or the SPI chip select module 205 and/or the UART chip select module 206.

[0099] Furthermore, the FPGA 21 incorporates the interfacing functions between the extension interface from the processor on the base module, the extension interface to the next extension module and all the local slave devices. All signals go through the FPGA, by this repeating the signals, ensuring optimal signal integrity to the base module or every next extension module, enabling robust communication.

[00100]The extension modules 2, 3 furthermore comprise a local UART slave device or module 22, connected via a local UART interface 220. This can be, e.g., a GPS transceiver, an RS232 interface transceiver, an RS485 bus transceiver.

[00101]The extension modules 2, 3 also comprise a first and second I2S audio codec 23, 24, exchanging respective bidirectional signals 2300, 2400 with respective first and second local I2S interfaces 230, 240. They convert digital serial audio streams (industry standard I2S protocol) to analog audio and vice versa. Each I2S audio codec 23, 24 provides two analog mono inputs channels and two analog mono output channels.

[00102] The extension modules 2, 3 comprise a local SPI bus 25 connected via a local SPI interface 250. The local SPI bus 25 contains several slave devices or modules (e.g., memory, IO expanders, displays). The SPI signals can be routed from the processor on the base module by the dynamic SPI multiplexer module 201. The chip select signals selected with the SPI chip select module 205 are general purpose outputs of the I2C IO extender 202. The communication is transparent for the OS on the processor of the base module because any GPIO can be configured in the slave device’s driver to be used as the chip select.

[00103] The extension modules 2, 3 furthermore each comprise local user IO 26. These are in- and outputs from the I2C IO extender 202, which can be used for external user IO or on-board control signals such as SPI slave device chip select signals. These IO can be set/read by the processor 10 of the base module through memory mapped IO as is common in many existing I2C IO extender IC’s. [00104]The extension modules 2, 3 comprise a local I2C bus 30 containing a number of slave devices or modules (e.g., memory, IO expanders, displays) and connected to the local I2C module 204 via a 2W connection 3000. Minimally an EEPROM module 302a, 302b and, in this example, an EEPROM programming connector 301 are present on the bus. The attached devices can be reached by the processor of the base module as if they were connected directly to the processor. The I2C address translation module 203 translates the addresses of the local slave devices to another address to make sure there are no address conflicts for the processor, even if the same address is used by slave devices on multiple extension modules attached to the same base module. [00105]The extension modules 2, 3 furthermore each comprise an EEPROM programming connector 301 enabling to store the extension module’s configuration in the EEPROM module 302 during extension module production, and the actual I2C EEPROM module 302a, 302b, each being I2C EEPROM slave devices. This memory device contains the extension module’s configuration. It defines, first of all, the I2C address translation mask used by the I2C address translation module 203. It also defines the configuration for the SPI chip select module 205, ensuring the dynamic SPI multiplexer module 201 is switched to the local bus when a local SPI slave is addressed. Furthermore, it defines the configuration of the UART chip select module 206, ensuring the dynamic UART multiplexer module 207 is switched to the local UART when the local UART interface is addressed by setting a defined output of the I2C IO extender 202. It also defines the configuration of the static TDM multiplexer module 208, particularly the routing of the TDM slot to I2S slot multiplexing. It also defines specific configurations for the I2C IO extender 202 (e.g., debounce parameters, default output states).

[00106] The extension modules 2, 3 also comprise local I2C slave devices 303 (e.g., memory, IO expanders, displays).

[00107]The extension modules 2, 3 comprise a dynamic SPI multiplexer module 201. This is a ‘switch’ switching the SPI signals coming from the processor on the base module over the extension interface to either the local SPI bus, or the SPI interface to the next extension module. The switching is done by the SPI chip select module 205 based on the chip select I2C IO extender 202 output defined by the extension configuration in the I2C EEPROM 302a, 302b. This makes communication between processor and SPI slave device transparent for the OS run by the processor without any modification to the standard SPI slave device’s device driver. If the local bus is not selected, the signals from the processor on the base module are routed to the next extension module.

[00108]The extension modules 2, 3 comprise an I2C IO extender 202. This function makes extra logic lO’s available for the processor on the base module as it was a I2C slave device IO extender directly connected to the processor’s I2C bus. The I2C address translation module 203 translates the addresses of this IO extender so the same FPGA implementation can be used on all extension modules attached to the same base module without the need for a specific address configuration for the I2C IO extender per extension module. The IO extender is implemented as memory mapped IO as is common in many existing I2C IO extender IC’s. This makes the communication transparent for the OS on the processor of the base module without the need for specific custom device drivers (a generic one can be used). In examples, special features are added to this IO extender such as input debouncing 270 (parametrizable) with respect to input signals 2700 from user IO 26, and default output states 260 for output signals 2600 toward user IO 26. These special features can be configured during power-on by the self-configuration engine 209 defined by the extension configuration in the I2C EEPROM 302a, 302b.

[00109]The extension modules 2, 3 comprise an I2C address translation module 203. This function translates the address coming from the processor of the base module by means of X-OR-ing the received address bits with a mask, defined in the configuration instructions stored in the I2C EEPROM 302a, 302b. Doing so, the address translation module governs the access to the 4W path 72 and the 4W I2C interfaces 120, 120'. This happens on-the-fly, making it completely transparent for the processor. This means that any I2C slave device 303 on the extension modules appears to be attached on the processor’s I2C interface itself (with a different address), enabling the use of the standard provided device drivers in the OS without alteration.

[00110] In this example, the 4W I2C interfaces 120, 120' comprise a signal repeater functionality. In variants of this example (not considered further), the 4W I2C interfaces 120, 120' do not comprise such functionality.

[00111]The extension modules 2, 3 comprise a local I2C module 204 for conversion between 4W unidirectional signals, according to a push-pull I2C interface, and normal 2W I2C bidirectional signals, according to bidirectional open collector set-up. This converts the unidirectional push-pull I2C interface of the extension interface to normal (2W bidirectional open collector) I2C conversion. This is partially implemented in the FPGA 21 and partially discrete. The local I2C module 204 uses static volage offset means to sense signal direction. This enables normal I2C devices to be attached to the FPGA on the extension module 21 .

[00112]The extension modules 2, 3 comprise an SPI chip select module 205, also referred to as SPI chip select logic. This function switches the SPI multiplexer module 21 when required, e.g., when a slave device on the local SPI bus is to be addressed, thereby determining access to the SPI interfaces 150, 150'. This relates to the outputs 260 of the I2C IO extender 202, wherein the selection of which outputs to use is configured in the SPI chip select logic upon start-up by the selfconfiguration engine 209, based on the configuration instructions stored in the I2C EEPROM 302a, 302b.

[00113]The extension modules 2, 3 comprise a DART chip select module 206, also referred to as DART chip select logic. This function switches the DART multiplexer module 207 whenever a specific output from the I2C IO extender 202 is set, thereby determining access to the DART interfaces 130, 130'. Which output 260 from the I2C IO extender 202 is used is configured in the DART chip select logic upon start-up by the self-configuration engine 209, based on the extension configuration stored in the I2C EEPROM 302. Advantageously, to communicate with the DART slave device on a specific extension module, the processor 10 on the base module merely sets the corresponding output of the I2C IO extender 202. This enables using the standard provided DART device drivers in the OS.

[00114]The extension modules 2, 3 comprise a dynamic DART multiplexer module 207. This is a ‘switch’ switching the DART signals coming from the processor on the base module over the extension interface to either the local UART interface 220 or the UART interface 130' to the next extension module. The switching is done by the UART chip select module 206 based on the output 260 of the chip select I2C IO extender defined by the extension configuration in the I2C EEPROM 302. This makes communication between processor and UART slave device transparent for the OS run by the processor without any modification to the standard UART slave device’s device driver. If the local interface is not selected, the signals from the processor on the base module are routed to the next extension module (e.g., pass-through of processor’s debug information).

[00115]The extension modules 2, 3 comprise a static TDM multiplexer module 208. This function implements a ‘switch’, routing data from any of the 16 TDM slots comprised in the multiplexed audio signals 1400, 1400' coming from the processor on the base module, via the TDM audio interfaces 140, 140', to the respective I2S output signals and channels as defined by the extension configuration in the I2C EEPROM 302. The data signal 1400, 1400' from the processor to the extension modules (for the digital-to-analog converters) is also 1 :1 available for the next extension module, making it possible to use the same signal on multiple extension modules without increasing the throughput. In the other direction (signals from analog-to-digital converters), data from any of the I2S input signals and channels can be routed to respective TDM slots, to be received by the processor 10 on the base module as defined by the extension configuration in the I2C EEPROM 302. The TDM slots not used by local I2S signals are filled with the data on the respective TDM slots from the next extension module. This function is configured upon start-up by the selfconfiguration engine 209.

[00116]The extension modules 2, 3 comprise a self-configuration engine 209. This state machine foresees in the configuration of some extension module specific functionality. At start-up, the Self configuration engine 209 reads out the I2C EEPROM 302 memory content. It uses this data to configure which I2C IO extender 202 output is used as chip select for the local SPI slave devices 25 or UART slave device 22 used by the SPI and UART multiplexer module 205, 206. It furthermore uses the data to configure specific parameters of the I2C IO extender 202, such as input debouncing parameters and default output states. It furthermore defines masks for the I2C address translation module 203, as well as configuration parameters for the TDM multiplexer module 208. This makes it possible to reuse the complete FPGA design without any alteration on different extension modules and even attaching multiple extension modules with the exact same hardware to a base module, by only changing the content of the EEPROM memory.

[00117] The device 2 of this example comprises I2C repeater functionality within its 4W I2C interfaces 120, 120', making it particulary suitable for use in systems with long total path length and/or systems with a large number of devices 2. By concatenation of the device 2, robust systems may be built, with long total path length and/or with large number of devices 2. In case of a single device 2 and a single base module (not shown), a long path length may be realized over the connection between device 2 and base module. In case of a base module combined with more than one device 2, an effective daisy chain topology may be realized, as illustrated in Fig. 1 , with device 2 and 3 connected according to a daisy chain topology.

[00118] Example 2: second example device and system according to the invention [00119]This example relates to Figure 2, showing a second example device 2 according to the invention, relating to a second example system (not shown) according to the invention.

[00120]The example device and system are similar to those of Example 1 , and the example device may be used in either the first example system or the second example system. Conversely, in example variants, the example device of Example 1 may be used in each of the first or second example system. In this regard, the correspondence in reference numerals with Example 1 is provided for the sake of clarity yet is not to be construed as limiting this Example in any way, as Example 2 and Example 1 may relate to different example embodiments.

[00121] Particularly, Figure 2 illustrates the device 2, which may be the extension module 2 of Example 1 , thereby only showing interfaces and modules relating to I2C signals and TDM audio data. Thereby, the I2C path sections and the path consists of two respective 4W I2C routes 1200a- 1200a' and 1200b-1200b', each provided with a respective I2C repeater module 120a, 120b, a respective I2C address translation module 203a, 203b connected thereto, and a respective local I2C module 204a, 204b. The latter connect between the respective address translation module 204a, 204b and respective 2W local I2C circuitry 303, 302a, 302b connected on a 2W I2C local line or bus 3000a, 3000b, for converting between 4W unidirectional signals from the address translation module and 2W bidirectional signals for the 2W I2C local line or bus 3000a, 3000b. Thereby, the first respective route 1200a-1200a' is for control (e.g., temperature sensor reading, EEPROM programming, audio codec configuration), and connects to miscellaneous I2C devices 303 at relatively lower speed. The second respective route 1200b-1200b' is for relatively higher speed, i.e., for speed IO, with an interrupt line, where specific lO's can subscribe to via the GPIO 2600, 2700, being a twenty wire line, connected to the route via an I2C IO extender with debouncing 202b. Also said 2W local I2C circuitry may relate to higher speeds, such as the EEPROM module 302a, 302b.

[00122]The TDM-related module 208a illustrated in Figure 2 may relate to the combination of the TDM multiplexer module 208 and the I2S interfaces 230, 240 of Example 1 , connecting to 4W lines 1400, 1400' carrying 16 multiplexed channels, on the one hand, and two 2W lines 2300, 2400 for I2S audio data.

[00123] Example 3: third example device and system according to the invention

[00124]This example relates to Figure 3, showing a third example device being an extension module 2 as part of an example system according to the invention. As shown, the system further comprises a further example device being a further extension module 3, and a base module 1 comprising the application processor 10.

[00125]The example device and system are similar to those of Example 1 and 2, so the example device may be used in any of the first, second or third example system or the second example system. Conversely, in example variants, the example device of Example 1 or 2 may be used in any of the first, second or third example system, with correspondence in reference numerals provided merely for the sake of clarity, and not to be construed as limiting.

[00126] Particularly, Example 3 highlights, through the example set-up of Figure 3, how a 4W-based I2C distribution means 7, relating to the devices and systems of Example 1 and 2, provides a transparent 2W I2C connection between a processor 10 and multiple I2C slave devices 303, without the processor 10 and the slave devices 303 being aware of the I2C distribution means 7 being 4W- based.

[00127]As illustrated, this requires a processor-side conversion 71 between 2W and 4W, on the one hand, and a device-side conversion 73 between 4W and 2W, on the other hand, and the 4W path 72 connecting them. This relates to a respective second static voltage offset (SVO) means 71 , corresponding to reference numeral 16 in Example 1 , and a (first) static voltage offset means 73, roughly corresponding to the local I2C module 204 in Example 1.

[00128] In its interaction with the I2C distribution means 7, the processor 10 takes up the role of I2C master 70. The 2W signals originating from the processor are converted to 4W with the processorside conversion 71 that comprises discrete components, amounting to second SVO means 71. In essence, a single transistor per I2C line, and thus two transistors to go from 2W to 4W, suffices. The processor and the processor-side conversion reside in the base module 1 . The path 72 carries unidirectional I2C 4W signals across the different extension modules 2, 3, hence residing in each of these modules, and the connectors therebetween. The device-side conversion 73 resides within the respective extension modules 2, 3, and comprises some logic belonging to the FPGA 21 , on the one hand, and discrete components for implementing a comparator outside of the FPGA 21 , as illustrated on Figure 3. Thereby, the FPGA also houses the address translation module 203, being integrated with the circuit portions responsible for device-side conversion 73. The slave device 303, finally, interacts with the I2C distribution means in the role of I2C slave, typically with open drain output. The respective slave devices 303 reside on respective extension modules 2, 3.

[00129] As illustrated in Figure 3, the FPGA further comprises unidirectional buffers for connecting to the unidirectional signals on the path 72; thereby unidirectional buffers of the first extension module 2 may be different from those of further extension modules 3.

[00130] Example 4: various example embodiments of the device of the invention

[00131] Figure 4 shows various example embodiments 2, 2', 2" of the device of the invention. Each of the devices is suitable to be connected to a base module 1 , and, optionally, to one or more further devices (not shown). Each of the example devices 2, 2', 2" is suitable from mediating between 4W unidirectional signals 1200, 1200' carried over the path toward an application processor (not shown, "uplink"), and, if present, another device (not shown, "downlink"). Each of the embodiments of the device may be provided with one or more of an address translation module, a TDM multiplexer module, an I2C IO extender, an SPI chip select module, a DART chip select module. Also, in other aspects, the device 2, 2', 2" may be similar to the device 2 of Example 1 .

[00132] Thereby, Fig. 4A illustrates an example device 2 similar to the device 2 of Example 1 , with a 4W I2C interface 120, 120' comprised within the device. In case of Example 1 , this relates to 4W I2C interfaces comprised within the FPGA 21 ; in this example it may relate to any hardware implementation. The device 2 of this example comprises I2C repeater functionality within its 4W I2C interfaces 120, 120', making it particulary suitable for use in systems with long total path length and/or systems with a large number of devices 2. By concatenation of the device 2, robust systems may be built, with long total path length and/or with large number of devices 2. In case of a single device 2 and a single base module, a long path length may be realized over the connection between device 2 and base module. In case of a base module combined with more than one device 2, an effective daisy chain topology may be realized, with the device 2 as building block, as illustrated by, e.g., Example 1 .

[00133] Fig. 4B, on the other hand, illustrates and example device 2' without any I2C repeater functionality comprised within the device. Instead, the FPGA 21' does not comprise repeater functionality, and connects, within the device 2', to the path section that runs through the device, at connecting points 122 and 123. In the example of Fig. 5B, opposed to Example 4, I2C repeater functionality is provided separately from the device, with a pair of I2C repeater modules 126. By concatenation of the assembly of device 2' and I2C repeater modules 126, robust systems may be built, with long total path length and/or with large number of devices 2'. In case of a single device and a single base module, a long path length may be realized over the connection between device and base module. In case of a base module combined with more than one device 2', an effective daisy chain topology may be realized, with the assembly of device 2' and I2C repeater modules 126 as building block. In another variant of the example of Fig. 4B (not shown), the pair of I2C repeater modules 126 is also comprised within the device 2'.

[00134] Fig. 4C, finally, considers an example device 2" that does not include I2C repeater functionality and does not have the path running though the device 2". Instead, the I2C path section comprised in the device is connected to an auxiliary I2C path section. The 4W unidirectional signals 1200, 1200' are carried to and from the device 2" over said auxiliary path section that extends between connections points 124 and 125 on the main path and device pins provided on the device 2". Within the device 2", the I2C path section connects to the device pins. Like in the example of Fig. 4B, I2C repeater functionality is provided separately from the device, with a pair of I2C repeater modules 126. By concatenation of the assembly of device 2" and I2C repeater modules 126, robust systems may be built, with long total path length and/or with large number of devices 2". In case of a single device 2" and a single base module, a long path length may be realized over the connection between device 2" and base module. In case of a base module combined with more than one device 2", an effective daisy chain topology may be realized, with the assembly of device 2" and I2C repeater modules 126 as building block.

[00135] (End of Example 4)