This invention relates to integrated squaring circuits and seeks to provide a circuit for producing an output signal which, except perhaps for an additive constant, is proportional to the square of an input signal and which is substantially independent of ordinary fluctuations in power supply voltage.

In telecommunication systems, squaring circuits— i.e., circuits which produce an output which is proportional to the square of an input—are useful in a variety of contexts. Since squaring a sine wave doubles its frequency, a squaring circuit is useful for shifting the frequency of an incoming carrier wave modulated by a signal to a higher frequency range or band. Such shifting is useful, for example, in_ a modem in which it is desired to process an incoming signal from a transmission channel in which the information is transmitted by phase-shift- keying modulation of the carrier, i.e., by imposing phase shifts upon the carrier wave at regular time intervals

(T) . The magnitude of each such phase shift can be one of a number of discrete possible amounts, illustratively four, each of these possible amounts of phase shift representing a different possible symbol of information being transmitted. Illustratively, the carrier has a frequency of 1200 Hz, and the phase shifts are imposed every 1/600 second. Thus, illustratively the transmission of information occurs at a symbol frequency or rate of 600 Hz(=1/T). In order to demodulate the incoming signal and thus to detect the symbols being transmitted by the channel, it is necessary to detect the magnitude of each of the phase shifts on the carrier. In so doing, it is desirable to have a circuit arrangement for squaring the incoming signal in order to produce a signal with frequency components at the symbol rate (1/T) representing the stream of phase shifts; bandpass filters are then used

to remove the carrier wave while preserving the symbol rate information. Illustratively, a bandpass filter centered at the symbol frequency (of 1/T = 600 Hz) can be used, whereby the carrier frequency (1200 Hz) is doubled (to 2400 Hz) and is suppressed by the filter, while the symbol rate information (600 Hz) is passed through the filter. Ordinarily, the carrier frequency is higher than the symbol rate. Therefore, since squaring a carrier wave doubles its frequency (but leaves the symbol rate the same), squaring the incoming signal before filtering is thus useful for doubling the carrier frequency (from 1200 to 2400 Hz) and thus separating the carrier further in frequency from the symbol rate (600 Hz). A narrow bandpass filter (i.e., with a quality Q of typically about 10 or more) centered at the symbol rate will then be able to remove more nearly completely the carrier wave component, thus doubled (or more) in frequency, from the symbol rate components, since such a bandpass filter in general more completely removes components whose frequencies are more distant from the center frequency of the pass band. After the original incoming signal (carrier with phase shifts) has thus been squared and filtered, the remaining symbol rate components are relatively free from any carrier and thus are available for further processing. In the foregoing squaring of the incoming signal, it is important that the squaring be pure and hence not yield an -significant amount of first harmonic (fundamental) component (at 1200 Hz)? otherwise the desired frequency separation of symbol information from the carrier will not be as complete as desired, and hence the symbol information emanating from the bandpass filter will be undesirably contaminated with the carrier.

To clarify the problem, it is known that a squaring circuit's principle of operation is governed by the trigonometric identity:

2(cos ωt)2 = 1 + cos 2 ωt (1)

where ω is the radian frequency, i.e., ω=2τrf where f_ is the cycle frequency. Thus, squaring a carrier signal of frequency produces a d.c. component and a second harmonic component (cos 2ωt) , but no first harmonic. On the other hand, a trigonometric identity such as:

4(cos ωt)^ = 2cos ωt + COS 3ωt (2)

shows that cubing the input (i.e., raising the input to the third power) results in an undesired first harmonic (as well as third harmonic) component in the output. Similarly, any odd integral power component in the output causes the output to contain undesired first harmonic. Thus a desirable squaring circuit does not produce any substantial amount of linear component, or any substantial amount of odd integral power components, in the output relative to the input.

In a paper by O. A. Seriki and R. W. Newcomb entitled "Direct-Coupled MOS Squaring Circuit," published in IEEE Journal of Solid-state Circuits, Vol. SC-14, pp. 766-768 (1979), a squaring circuit is described using MOS (metal oxide semiconductor) transistor technology. That circuit, however, successfully, removes the undesired linear term only if the voltage supplies ( and

V ) for the transistors in the circuit are carefully controlled and adjusted during operation so that (V_ _D + _sς ) is essentially zero. For example, V _nn = +4.0 volts and V = -4.0 volts. But, such control of voltage supplies would necessitate the addition of undesirably complex control circuitry, because in the present state of the art the ordinary voltage source fluctuates by as much as 5 percent during operation, and such voltage fluctuations would produce an undesirable corresponding amount, as much as about 1 _. 00 percent, first harmonic in the output of that squaring circuit.

Therefore, it would be desirable to have a

squaring circuit whose output is substantially devoid Of first harmonic (i.e., the linear component) even in the presence of voltage supply fluctuations of as much as about +_10 percent, i.e., well above the amount of ordinary fluctuations. By "substantially devoid" it is meant that less than about 5 percent first harmonic amplitude relative to second harmonic is present in the output.

According to this invention an integrated squaring circuit includes a pair of substantially identical dual-ended substantially linear amplifiers, each for receiving an incoming signal and each having separate coupling means for feeding a different one of a pair of substantially identical dual-to-single-ended substantially linear converters, the coupling means of one of the amplifiers cross-coupling a pair of outputs of that amplifier to a pair of inputs of the corresponding converter, and a nonlinear/summing device for nonlinearly transforming and summing the single-ended outputs of the converters. By "nonlinear/summing ^" device" is meant a device that nonlinearly transforms each of the single-ended outputs—say of amplitudes A and B, respectively—of the converters in substantially the same way and adds the results together. For example, a "squarer/summer" device is one which squares each of these single-ended outputs of amplitudes A and B, and adds the results together to produce an output equal to 8(A ^ώ 9 + B9), where 8 is a constant. In general, a nonlinear/summing device having a nonlinear transformation function F produces an output which can be represented as β[F(A) + F(B)].

In a specific embodiment of the invention, each amplifier is a difference amplifier comprising a pair of MOS inverters mutually connected in parallel. Each amplifier is supplied by the same constant current source. One of the MOS inverters receives the incoming signal, and the other receives a steady reference voltage (such as ground) . Each dual-to-single-ended converter comprises a

separate pair of input MOS transistors and a separate pair of output MOS transistors. Each input MOS transistor is connected in series with a different one of the output transistors, the gate terminals of the output transistors in each converter being connected together and to the same one of the input transistors. Finally, the squarer/summer network comprises a pair of input MOS transistors connected in parallel with each other and in series with an MOS transistor load, the gate terminal of one of these input transistors being connected to the output terminal of one of the dual-to-single-ended converters and the gate terminal of the other of these input transistors being connected to the output terminal of the other of the dual- to-single-ended converters. By "MOS transistor" is meant an insulated gate field effect transistor having a metal xide (or other insulator) jsemiconductor structure, as known in the art.

In this way, as much as about a +_10 percent fluctuation in the bias voltage supply can be tolerated without introducing any more than 5 percent undesirable first harmonic amplitude into the output of the squaring circuit.

The invention will now be described by way of example with reference to the accompanying drawing, in which:

FIG. 1 is a block function diagram illustrating an integrated squaring circuit embodying the invention; and _ FIG. 2 is a schematic diagram of an integrated squaring circuit embodying the invention. Referring now to FIG. 1, an integrated circuit arrangement 100 for squaring an incoming input signal receives the incoming signal V at a circuit input terminal 101 and delivers an output at a circuit output terminal 102. By means of interconnecting wires, the input' signal V is delivered from the input terminal 101 to positive input terminals 111 and 121, respectively, of first and second

difference amplifiers 110 and 120, respectively; whereas ground potential is delivered to negative input terminals 112 and 122, respectively, of these amplifiers. By "ground" is meant a steady voltage reference with respect to which the incoming signal varies with time. The first amplifier 110 is constructed substantially identically to the second amplifier 120, and both amplifiers are advantageously substantially linear in their outputs versus inputs. Each of these amplifiers is dual-ended at both input and output ends, that is, each amplifier has two input terminals and two output terminals, as described more fully below. A positive output terminal 113 of the first amplifier 110 is connected to a positive input terminal 131 of a first dual-to-single-ended converter 130, and a negative terminal 114 of the first amplifier 110 is connected to a- negative terminal 132 of the first converter 130. On the other hand, for cross- coupling the second amplifier 120 to the second dual-to- single-ended converter 140, a positive output terminal 123 of the second amplifier 120 is connected to a negative input terminal 142 of a second dual-to-single-ended converter 140, and a negative output terminal 124 of the second amplifier 120 is connected to a positive input terminal 141 of the second converter 140. The first and second converters are also constructed to be substantially identical.

An output terminal 133 of the first converter 130 is connected to an input terminal 151 of a squarer/summer 150, and an output terminal 143 of the second converter 140 is connected to another terminal of the squarer/summer 150. An output terminal 153 delivers output of the squarer/summer 150 to an input terminal 161 of an inverter 160, and the inverter delivers to the output terminal 102 the desired output signal representative of the square of the input signal V . It should be noted that may contain components of higher even-integer powers (and hence even harmonics) of

the input but substantially no linear or other odd-integer power (odd harmonic) components. The inverter 160 can be omitted, and the output of the squarer/summer 150 is then the desired output. During operation, because of the substantial linearity of the amplifiers 110 and 120, a positive-going increment ^7 in the input signal V_ produces corresponding positive-going increments in voltage αv on the positive output terminals 113 and 123 of the amplifiers 110 and 120, respectively, and corresponding negative-going increments (-αv) on the negative output terminals 114 and 124, where α is a constant (independent of v) . In response, the first converter 130 develops a positive-going increment on its output terminal 133 owing to the positive or direct (positive output terminal 113 to positive input terminal 131) coupling between the first amplifier 110 and the first converter 130, whereas the second converter 140 develops a negative-going increment on its output terminal 143, owing to the negative or cross- coupling (positive output terminal 123 to negative output terminal 142) between the second amplifier 120 and the second converter 140.

The squarer/summer 150 operates by squaring the signals on its input terminals 151 and 152, and then by adding these squares. For example, denoting the voltage developed on the output terminal 133 of the first converter 130 by (V + αv) , where V is an offset and v is the increment in the input signal, then the voltage on the Output terminal 143 of the second converter 140- will be (V - αv) because of the substantial linearity of response of both first and second amplifiers, the substantial identity of construction of the first amplifier relative to the second amplifier, the substantial linearity of both the first and second converters, and the substantial identity of construction of the first converter relative to the second converter. Squaring and adding these voltages by the squarer/summer 150 yields (V + αv) ² + (V - αv) ²

2 9 + 2αa9*v9, that is, there is"no linear term in the increment v.

More generally, the squarer/summer 150 can be any nonlinear/summer device element that produces an output which is equal to F(αv) + F(-αv) , i.e., the sum of the nonlinear function F(αv) of the increment αv and the nonlinear function F(-αv) of the negative increment -αv. Expressed as a Taylor series:

F(αv) + F(-αv) =

{A + aαv + b(αv) ² + c(αv) ³ + d(αv) ⁴ + ...} +

{A + a(-αv) + b(-αv) ² + c(-αv) ³ + d(-αv) ⁴ + ...}

* 2A + 2aα ² v ² + 2cα v ⁴ , (3)

where A is the contribution of each of the outputs when the increment v=o, and a,b,c, and d are the coefficients of the power series expansion of each of the inputs being processed by the device element. The significant point herein is the cancellation of the linear aαv and aα(-v), and of the third-order terms, c(αv) ^J and c(-αv) , as well as the cancellation of all other higher order odd- integer power terms.

FIG. 2 is a circuit schematic of a specific circuit 200 embodying the integrated circuit 100 described above. Elements of FIG. 2 which are equivalent to those of FIG. 1 are denoted by the same reference numerals plus one hundred. All transistors in FIG. 2 advantageously are N- channel enhancement mode MOS, except for M33 which is P- channel enhancement mode MOS. The circuit 200 has an input terminal 201 and an output terminal 202.

The first difference amplifier 110 ( ^" FIG. 1) is formed in the circuit 200 (FIG. 2) driver transistors M11 and M12, together with load transistors M13 and M14, as well as a current source transistor M15. Advantageously,

the channel width-to-length ratios (W/L), and hence the transconductances, of the drivers M11 and M12 are selected to be mutually equal to that of the loads M13 and M14, in order to achieve unity gain of the difference amplifier, but this selection is not essential. The driver M11 is connected in series with the load M13 to form a first branch of the difference amplifier 210, whereas the driver M12 is connected in series with the load M14 to form a second branch of the first amplifier in parallel with the first branch. These first and second branches are connected in series with the current source transistor M15 which provides a constant current to the branches. The gate terminal of the driver M11 is connected to the input terminal 201; the gate of the driver M12 is connected to ground (i.e., substrate ground). The gate and drain terminals of the load transistors M13 and M14 are connected to a first power line 203 which is maintained during operation at a steady voltage V of typically about +5.0 volts, i.e., about 5.0 volts above ground potential. The source terminal of the current source transistor M15 is connected to a second power line 204 maintained during operation at a steady voltage V _gs of typically about -5.0 volts, i.e., about 5.0 volts below ground potential. The gate terminal of this current source transistor M15 is connected to a bias voltage line 205 which is maintained during operation at a bias voltage

VN„B_ suitable for causing the N-channel MOS current source transistor M15 -to deliver a constant current. For example, this bias voltage V can be supplied by the bias current reference circuit described in ϋ. S.

Patent 4,342,926. This bias voltage V can also be simultaneously used as a reference for other elements of a signal processor, such as a modem, of which the squaring operation is only a part. The gate terminal 211 of driver M11 serves as a positive input terminal of the first difference amplifier, and the gate terminal 212 of driver M12 is connected to

(substrate) ground. The nodes 213 and 214 serve as positive and negative output terminals, respectively, of this first amplifier.

The second difference amplifier 120 (FIG. 1) is formed in the circuit 200 (FIG. 2) by drivers M21 and M22, loads M23 and M24, and current source M25. This second amplifier is substantially identical to the first difference amplifier, and corresponding transistors of this second amplifier have been denoted by the same numerals as those of the first amplifier plus ten.

By locating the transistors of the first and second difference amplifiers in relatively close material proximity on the surface of the same semiconductor body, in ^• which the circuit 200 is integrated, the desired substantial identity of operating characteristics of the amplifiers can be assured in the face of variations in temperature and semiconductor processing parameters across the surface of the body. Similarly, the substantial identity of the two converters can be achieved. The first dual-to-single-ended converter 130

(FIG. 1) is formed in the circuit .200 (FIG. 2) by transistors M16, M17, M18, and M19. Transistors M16 and M17 serve as drivers of the loads formed by transistors M18 and M19, respectively. The gate terminal of M18 is connected to its drain terminal; the gate terminal of M19 is connected to the gate terminal of M18. The gate terminal 232 of M16 is connected to the negative output terminal 214 of the first difference amplifier, and the gate terminal 231 is connected to the positive output terminal 213 thereof.

During operation, a positive-going incremental signal v _^ in the input V causes transistor M11 to become more conducting and to draw more current from the source M15, whereby the current in the first branch of the first amplifier increases, and in the second branch decreases. Accordingly, the voltage at terminal 214, and hence at terminal 232, decreases away from VΓJD

whereas the voltage at the node 213, and hence also at the node 231, increases toward V . In turn, the resistance of M16 increases, whereby the voltage at terminal 235 between M16 and M18 decreases (toward V _cc ), and hence the resistance of M19 increases. At

DO the same time, the increased voltage at terminal 231 causes the resistance of M17 to decrease. As a result of this decrease in resistance of M17 and the increase in resistance of M16, the voltage at terminal 233 increases. Thus, a positive-going input signal V produces a positive-going response at terminal 233, serving as the output terminal of the first dual-to-single-ended converter.

Similarly, the second dual-to-single-ended converter 140 (FIG. 1) is formed in the circuit 200 (FIG. 2) by transistors M26, M27, M28 and M29, respectively. The positive output terminal 223 of the second difference amplifier is located between M22 and M24, and the negative output terminal 224 of the second difference amplifier is located between M21 and M23. Note, however, that terminals 223 and 224 are connected to the gate terminals 242 and 241, respectively, of M26 and M27, respectively, instead of vice versa, and also note that the output terminal 243 of this second converter is located between M27 and M29, rather than between M26 and M28, in order to provide the cross-coupling of the second difference amplifier to the second dual-to-single ended • converter. During operation, a positive-going input signal V produces a negative-going signal at terminal 241 (and a positive-going signal at terminal 242). Thus, a positive-going input signal V produces a corresponding negative-going signal at terminal 243, serving as the output terminal of the second dual-to- single-ended converter. The squarer/summer 150 (FIG. 1) is formed in the circuit 200 (FIG. 2) by transistors M30, M31 , and M32. The transistors M31 and M32 serve as drivers; the

transistor M30, as a load, with its gate terminal connected to its drain terminal. The output terminals 233 and 243 of the first and second converters, respectively, are connected to the input terminals 251 and 252, respectively, of the squarer/summer 150, i.e., to the gate terminals of drivers M31 and M32, respectively. The output of this squarer/summer is developed at terminal 253. Finally, the inverter 160 (FIG. 1) is formed in the circuit 200 (FIG. 2) by transistors M33 and M34. The gate terminal of M33 is connected to the output terminal 253 of the squarer/summer; the gate of M34 is connected to its drain. A node between M33 and M34 forms an output terminal of the inverter and hence of the circuit 200. Transistors M31 and M32 are advantageously biased in their nonlinear (saturation) operating regions, that is, the voltages at their (gate) nodes 251 and 252 should be maintained during operation at values which are sufficiently small (above V_ ) so that they do not exceed the drain-source drop plus threshold voltage of the respective transistors M31 and M32. Ordinarily, the nonlinear (saturation) regions of M31 and M32 yield currents which are quadratic in the respective gate voltages less threshold voltages, as well known in the art. Proper choice of the channel width-to- length ratios of the various transistors which influence the voltages on these nodes 251 and 252 can ensure this nonlinearity of operation of these transistors M31 and M32. During operation, a positive-going increment v_ in the input signal V produces a positive-going response at terminal 233 and a negative-going response at terminal 243. Thus, the voltage at the gate terminal 251 of M31 goes up by an increment v_, and the voltage at the gate terminal 252 of M32 goes down by an equal (but opposite) increment, -v, so long as the constructions of the second amplifier and the second converter are identical with those of the first amplifier and of the first converter, respectively (except for the above-mentioned cross coupling) . In turn, the resistance of M31 decreases;

that of M32 increases. To the first order approximation in v, therefore, the voltage at the output terminal 253 of the squarer/summer does not change, but to the second order, it does, because of the nonlinearity of the operating regions of M31 and M32. Thus, the gate terminal 261 of the driver M33 of the inverter receives response signal of order v , and the inverter (which is optional) serves to amplify this response. Conversely, a negative-going increment (-v) of input signal V_ _N produces a negative-going voltage response at terminal 251 and a positive-going response at terminal 252, but produces the same second-order response at terminal 253 for the same ^• increment v; in V_ regardless of the polarity (sign) of the increment. For the sake of illustration, typical values of channel width-to-length ratios (W/L) for the transistors are: M11=M12=M21=M22=M13=M14=M23=M24=10/38, Ml6=M17=M26=M27=8/97, M30=10/65, M31=M32=17/60, M18=M19=M28=M29=10/13, M15=M25=40/8, M33=22/15, M34=10/42.