Background of the Invention Integrated circuits or ICs are extensively used in all types of today's electronic devices. ICs are typically designed to operate in a particular manner to perform particular functions. Because of this, many different ICs are generally necessary for a modern electronic device to operate. The ICs of a modern electronic device must be able to cooperate with one another in order to orderly communicate (receive and/or transmit data/information) to one another.

Cooperation and communication in an IC environment includes the ability of an IC to send data/information to other ICs typically in response to a query signal from another IC and/or to receive data/information from other ICs. This is typically achieved by providing a communication link or channel between the ICs such that the ICs are in communication with one another. One way to efficiently provide the communication link is via a bus structure. A bus structure is essentially a common communication channel for the plurality of ICs in the electronic device.

One such bus system/structure is known as an Inter Integrated Circuit bus or the 12C bus (interchangeably, the 12C bus). The 12C bus system/structure operates

on an 12C protocol that allows the plurality of ICs to be connected to and in communication with one another over a bus structure. 12C was developed by Philips Semiconductor to provide a way to connect (i. e. provide communication between) a central processing unit (CPU) and associated peripheral ICs within a television environment.

12C is, in particular, a serial bus system/protocol that allows various ICs within a device to communicate with one another. In the implementation of 12C, each IC, (i. e. a device, driver, memory, or complex function IC/chip), or the like is assigned a unique address. The 12C system can then send and/or receive data to/from a particular IC by using its address. In maintaining the integrity of 12C, when a new IC is developed, the designer must apply for and obtain a unique IC address for and from the 12C authorizing/issuing entity (i. e. Philips Semiconductor). This allow for the 12C system to grow as more types of addressable devices/lCs are uniquely registered. The unique IC address is then hardwired internal to the IC. Philips Semiconductor maintains these addresses (otherwise known as"slave addresses") in a registry or the like to assure integrity of the assigned addresses. However, ICs may have the same address for various reasons. As well, a particular device or IC may use the same address. If this occurs, bus contention problems may arise. The described problem is discussed in more detail below.

What is therefore needed is a system and method for obviating bus contention resulting from devices or ICs having commonly assigned addresses in an 12C environment.

Summary of the Invention The present invention is an apparatus, system and method which provides for the modification or programmability of an address of an 12C device. The modification or programming may be accomplished via an input signal received by an 1/0 terminal of the device. In another form, the present invention also provides for substantially simultaneous modification of first and second addresses of respective first and second 12C devices. The modification or programming may be accomplished via an input signal received by an 1/0 terminal coupled to both the first and second 12C devices.

The present invention obviates bus contention problems in an 12C bus/protocol system due to IC address conflict through the ability to modify (change) or program the 12C address. Modification or programming can be accomplished during the design phase or thereafter via software.

By permitting programming an IC's address, an address may be chosen that obviates an address conflict. The address of the IC or components thereof is determined by a signal applied to an 1/0 pin of the IC.

In one form, the present invention is an integrated circuit comprising a plurality of 1/0 terminals, circuitry in communication with selective ones of the plurality of 1/0 terminals, and an 12C interface in communication with the circuitry, the aid 12C interface having a modifiable address.

In another form, the present invention is an integrated circuit system. The integrated circuit system comprises a first device with a first 12C interface, the first 12C interface having a first defined address, a second device with a second 12C interface,

the second 12C interface having a second defined address, and means for substantially simultaneously changing the first and second defined addresses.

In yet another form, the present invention is a method of modifying first and second defined addresses in an integrated circuit system wherein the integrated circuit system has a first device with a first 12C interface having a first defined address, and a second device with a second 12C interface having a second defined address. The method includes a) providing a control signal to a first address input of the first 12C interface, b) providing the control signal to a second address input of the second 12C interface; and c) substantially simultaneously changing the first defined address and the second defined address in response to the control signal.

Brief Description of the Drawings Reference to the following description of the present invention should be taken in conjunction with the accompanying drawings, wherein: Fig. 1 is a diagram of an exemplary integrated circuit system in communication with one another via the 12C bus/protocol system in which the present invention may be utilized ; Fig. 2 is an upper level block diagram of one of the integrated circuits of the exemplary integrated circuit system of Fig. 1, the chosen integrated circuit having two internal blocks of circuitry/logic each of which has been assigned and configured for a particular address in the 12C bus/protocol system and which has been modified in accordance with the principles of the present invention as disclosed herein;

Fig. 3 is a simplified block diagram of an alternate embodiment of an addressable IC such as the IC of Fig. 2, in accordance with the principles of the present invention; and Fig. 4 is a table illustrating a manner of making 12C addresses modifiable or programmable.

Corresponding reference characters indicate corresponding parts throughout the several views.

Detailed Description of the Invention Referring now to Fig. 1, there is depicted a system, generally designated 10, that represents any system, but particularly an electrical system, in which a plurality of devices are in communication with each other via a common network, particularly a bus structure. It should be appreciated that while the system depicted in Fig. 1 is an electrical system and, more particularly, an integrated circuit system having a controller IC and a plurality of slave ICs all in communication with each other via a system bus and a bus management system, the principles of the present invention are applicable to other similar systems of an electrical and/or non-electrical nature.

The system 10 depicted in Fig. 1 is particularly an 12C bus/protocol system (12C system). The 12C system 10 includes a command issuing IC 12 in communication with an 12C bus, generally designated 18. The command issuing IC 12 may be known as a main IC which is operable to initiate data transfers on the bus 18, such as a CPU. The 12C system 10 further includes a plurality of slave ICs, generally designated 20, that are in communication with the 12C bus 18.

The 12C bus consists of a Serial CLock line (SCL) 14 and a Serial DAta line (SDA) 16. The SCL 14 is coupled to an 1/0 pin of the command issuing IC 12 and to an 1/0 pin of each slave IC 20 for supplying a serial clock signal to each slave IC 20.

The SDA 16 is coupled to another 1/0 pin of the main unit and to another 1/0 pin of each slave IC 20 for data transfer and general communication. Although the SCL 14 is bidirectional, the command issuing IC 12 controls/generates the system clock and thus the SCL 14 has a single-headed arrow to designate the nature of the clock signal line. The SDA is also bi-directional and thus has a double-headed arrow to designate the nature of the serial data line. Each of the slave ICs 20 is operable to receive protocol commands from the command issuing IC 12 and respond appropriately.

It should be appreciated that there may be more than one command issuing, or master, IC in the system 10. Thus, IC systems such as the system 10 may have various combinations of command issuing ICs and slave ICs.

In order to communicate with and between the plurality of slave ICs 20, each slave IC 20 is assigned a unique address. The unique address is hardwired into the respective slave IC 20 typically within an 12C bus interface section/circuitry/block.

The internal address of each slave IC 20 is thus fixed. Some of the slave ICs 20 have only one fixed address. Some of the slave ICs have more than one fixed address, typically due, at least in part, to having more than one internal 12C bus interface or integrated circuitry section each of which has a previously assigned 12C address. The principles of the present invention will be shown and described with reference to a dual or greater (multiple) fixed address IC.

It should be appreciated that the system 10 of Fig. 1 is only exemplary of an environment/application in which the present invention may be utilized. Preferably, the present invention is applicable to and used in any system of ICs that utilize the 12C protocol/bus structure/system. Of course, the present invention may be used in other similar protocol/bus structures/systems. The type of IC and IC system in which the present invention is utilized may take many forms and/or perform many functions.

The exemplary system 10 of Fig. 1, may be considered as the operation circuitry of a television signal processing device. A multiple address IC, operable to process television signals, is designated 20UL in Fig. 1. In particular, the exemplary IC 20UL provides television signal processing for a variety of formats of television signals from a variety of sources, and is known as a Universal Link IC (UL IC). The UL IC 20us is adapted/operable (i. e. includes appropriate circuitry/logic) to provide satellite television (digital) signal processing, terrestrial (including cable distribution) digital television signal processing, and terrestrial (including cable distribution) analog television signal processing in addition to other associated television signal processing. These analog and digital signals may be provided in various formats and modulation schemes. Of course, ICs utilizing the 12C protocol/bus that are adapted to perform other functions may utilize the principles presented herein.

Examples of other ICs/slave devices are designated 20a, 20b, 20c... 20N-1, 20N in Fig. 1. They represent all ICs or other addressable devices and/or components in communication with the bus 18. It is assumable that each of the ICs/slave devices 20a, 20b, 20c... 20N 1, 2ON have at least one address (an 12C address). In any IC system such as that shown in Fig. 1, however, there may be address problems wherein two (or more) ICs share the same fixed/assigned address.

This may arise during design of an IC that utilizes at least two blocks of integrated circuitry/logic having previously assigned addresses. The problem of same assigned addresses is obviated with the present invention during the design phase by hardwire programming or modification of at least one of the addresses. Same assigned addresses may also arise in the context of devices or software components being added to the IC system during operation thereof. In this case, same assigned addresses may be obviated by having software modification or programmability of the addresses.

This problem is obviated or alleviated by the present invention. In particular, the present invention provides a programmable 12C address in an IC. The programmable nature of the address, even though a fixed address has been previously assigned to the block of integrated circuitry, allows a designer of IC systems to change the"fixed"address of the IC to another address not otherwise used in the system.

Referring to Fig 2, a top level block diagram of the Universal Link (UL) IC 20UL is shown that is modified according to the principles of the present invention. The UL IC 20UL is an integrated circuit chip of mixed signal design, i. e. it includes analog signal processing circuitry/logic and digital signal processing circuitry/logic, for televisions, set-top boxes, and other similar devices that utilize/process analog and/or digital television signals. The UL IC 20UL also incorporates or integrates various analog and digital signal processing functions that were previously accomplished by separate ICs into a single IC. The integrated circuitry or blocks comprising the separate ICs or an interface section thereof were thus assigned addresses under the 12C protocol/system. The blocks or sections retain their previously-assigned fixed

address after consolidation because the design of these blocks is adopted without change from the design of the prior separate ICs, including without changing the design of the 12C interface section of each block. Thus, the UL IC 20UL inherently has two addresses.

However, in accordance with the present invention, the addresses of the sections of the UL IC 20us are able to be changed. In particular, one bit of the chip address is controlled by a control signal in order to designate or change the address to which the device will respond.

It should be appreciated that the Universal Link IC 20us is only representative of an integrated circuit/circuit chip that utilizes the 12C protocol/bus and that the principles presented herein are applicable to all types of integrate circuits and/or integrated circuit systems that utilize the 12C protocol/bus.

With continued reference to Fig. 2, the Universal Link IC 20uL includes three main sections, namely a"Satlink"section for demodulating satellite transmitted television signals, generally designated 30, a"VSB (Vestigal SideBand) link"section for demodulating terrestrially transmitted general digital and/or digital high definition (HDTV) signals (of which the HDTV signal can be modulated via any type of digital modulation scheme), generally designated 32, and a"DCD"section that provides switching, chroma demodulation, and other signal processing of NTSC (analog) signals, generally designated 34.

These sections operate independently and in parallel, but are supported by a common clock generator 50 that provides a plurality of clock signals 80 for the various sections of the IC 20UL. The clock generator 50 receives a clock signal from a Phase Locked Loop (PLL) synthesizer 48 that receives a clock signal from the SCL

14. The plurality of IC clocks 70 are utilized to clock the various integrated circuitry/logic of the sections 30,32, and 34 of the Universal Link IC 20UL. The Universal Link IC 20uL also includes a plurality of 1/0 (input/Output) pins, some of which are labeled by text in Fig. 2. The I/O pins extend to the exterior of the IC package or chip.

With continued reference to Fig. 2, the UL IC 20UL includes a first 12C bus/micro interface section 40 that is in communication with the 12C bus 18 and an internal bus 44. The first 12C bus/micro interface 40 is essentially a slave device (IC block or section) and includes appropriate circuitry/logic to provide communication between the other slave ICs 20 and the command issuing IC 12 that are in communication with the 12C bus 18, and the various portions of the Satlink section/circuitry/logic 30. The first 12C bus/micro interface 40 also has a previously assigned 12C address that is fixed internal thereto. The various blocks or portions of the Satlink section 30 communicate with the 12 C bus/micro interface 40 via the internal bus 44. An address bit input of the 12C bus/micro interface 40 (or other address receiving section/block) is coupled via a line 52 to an 1/0 pin 60 of the UL IC 20ut.

The UL IC 20uL further includes a second 12C bus/micro interface section 42 that is in communication with the 12C bus 18 and an internal bus 46. The second 12C bus/micro interface 42 is essentially a slave device (IC block or section) and includes appropriate circuitry/logic to provide communication between the other slave ICs 20 and the command issuing IC 12 that are in communication with the 12C bus 18, and the various portions of the VSB/DCD sections/circuits/logic 32 and 34. The second 12C bus/micro interface 42 also has a previously assigned 12C address that is fixed

internal thereto. The various blocks or portions of the VSB and DCD sections 32 and 34 communicate with the 12C bus/micro interface 42 via the internal bus 46. An address bit input of the 12C bus/micro interface 42 (or other address receiving section/block) is coupled via a line 54 to an)/0 pin 60 of the UL IC 20us.

The 12C bus/micro interfaces 40 and 42 are in communication with the 12C bus 18 in a known manner as represented by the arrows labeled"to 12C bus."In accordance with an aspect of the present invention, the address of the 12C bus/micro interface 40 is modifiable or programmable. As well, the address of the 12C bus/micro interface 42 is modifiable or programmable. The 12C bus/micro interface 40 includes a control line 52 that is in communication with the address input of the 12C bus/micro interface 40 and an)/0 pin or terminal 60. The 1/0 pin 60 is in communication with the 12C bus 18. The 12C bus/micro interface 42 includes a control line 54 that is in communication with the address input of the 12C bus/micro interface 42 and the)/0 pin 60. In one form, modification or programming of the respective addresses for the 12C bus/micro interfaces 40 and 42 is accomplished by supplying a control signal via the 1/0 pin 60. The 12C bus/micro interfaces 40 and 42 are responsive to the control signal such that their respective addresses are substantially simultaneously modified or programmed.

In one form, this is accomplished by coupling the control line 52 from the 1/0 pin 60 to an address input of the 12C bus/micro interface 40 and coupling the control line 54 from the 1/0 pin 60 to an address input of the 12C bus/micro interface 42. The control signal provided to the 1/0 pin 60 thus modifies or programs the addresses of the 12C bus/micro interfaces 40 and 42 via the control lines 52 and 54. More particularly, the control line 52 is coupled to the 12C bus/micro interface 40 such that

one bit of the address of the 12C bus/micro interface 40 is modified or programmed by the control signal. As well, the control line 54 is coupled to the 12C bus/micro interface 42 such that one bit of the address of the 12C bus/micro interface 42 is modified or programmed by the control signal. Since the control lines 52 and 54 are coupled to the same I/O pin 60, the addresses of the 12C bus/micro interfaces 40 and 42 are modified or programmed together.

The table 90 of Fig. 4 sets forth an illustration of the above principles and reference is now made thereto. It should be appreciated that while the table 90 refers to the Universal Link IC 20UL discussed above with respect to Figs. 2 and 3, the principles are applicable to all types of devices or integrated circuits that utilize the 12C system. In the table 90, the column 92 labeled"Section"refers to the UL IC 20UL Satlink block 30 and, more particularly, to the 12C bus/micro interface 40 thereof. In keeping with the above, it should be appreciated that the Satlink block 30 is representative of any device addressable in the 12C system. In the table 90, the column 92 labeled"Section"refers to the UL IC 20us VSB/DCD block 32/34 and, more particularly, to the 12C bus/micro interface 42 thereof. In keeping with the above, it should be appreciated that the VSB/DCD block 32/34 is representative of any device addressable in the 12C system. Therefore, the below discussion is applicable to all types of 12C devices and not applicable only to the Universal Link IC 20UL. It should be appreciated that the table 90 shows the four (4) possible addresses for two 12 C devices or slaves, denoted by the rows 93,95,97, and 99.

Specifically, one address is for a Satlink write (i. e. writing data to the Satlink block 30 via the 12C bus), one address is for a Satlink read (i. e. reading data from the Satlink block 30 via the bus), one address is for a VSB/DCD write (i. e. writing data to the

VSB/DCD block 32/34 via the 12C bus), and another address is for a VSB/DCD read (i. e. reading data from the VSB/DCD block 32/34 via the 12C bus). Column 98 indicates the full address for the particular sections when the"P"bit (programmable bit) is"0"or low (the first full address) and when the"P"bit is"1"or high (the full address in parentheses).

The addresses for the Satlink section 30 and the VSB/DCD section 32/34 consist of seven bits (which can be denoted B7, B6, B5, B4, B3, B2, and Bi, beginning with the most significant bit to the second least significant bit) plus an eighth bit (denoted Bo) reserved for indicating a read (R) or write (W) condition. The eight bits, B7, B6, B5, B4, B3, B2, B1 and Bo, combine to form a full eight bit address, column 98, in hexadecimal. As indicated in the table 90 the least significant bit (Isb), Bo, column 96, of the address is reserved for R/W indication. When the Isb of the address is"0", a write (W) is requested. When the Isb of the address is"1", a read (R) is requested.

In accordance with an aspect of the present invention, one of the seven bits (B7, B6, B5, B4, B3, B2, and Bi) of the eight bit address (since the Isb/Bo is reserved for R/W, column 96) may be modified or programmed. This is indicated in the 12C Chip address column 94 of the table 90 by the"P"designation. The"P"bit may be a zero/low ("0") or a one/high ("1") depending on which full address is to be utilized for the address of the particular device. If the"P"bit is tied low, a first address is defined for the particular 12C device. If the"P"is tied high, a second address is defined for the particular 12C device. The choice as to which address is utilized may be hardwired into the system, as by tying the lao pin 60 either high or low, or may be variable via software, e. g. by coupling the"P"bit pin of the IC to a software- controllable port of a control device such as a microcomputer. As indicated above,

since the programmable or modifiable bit is the same for the Satlink section 30 and the VSB/DCD section 32/34, the two addresses are modified, programmed, or changed substantially simultaneously. Thus, in any 12C system of two or more 12C devices, when the same"programmable"bit or bits is/are chosen, the two 12C devices will have their addresses modified at substantially the same time. Additionally, while the bit B2 is shown as the"P"bit, it should be appreciated that any of the seven bits B7, B6, B5, B4, B3, B2, and Bi, or any one of the bits not reserved for other purposes, may be the"P"bit.

In accordance with an aspect of the present invention, two 12C devices, such as the 12C bus/micro interfaces (12C slaves #1 & #2 in Fig. 3) 40 and 42, are interconnected so as to receive a common control signal and change their address substantially simultaneously. Specifically, since the programmable or modifiable bit "P"of the 12C addresses for the respective is the same for both the Satlink section 30 via the 12C bus/micro interface 40 and the VSB/DCD section 32/34 via the 12C bus/micro interface 42, the two addresses are modified, programmed, or changed substantially simultaneously.

The Satlink write chip address, row 93, shows the address used to indicate a write data/information to the 12C bus/micro interface 40 of the Satlink section 30. The bits B7, B6, B5, B4, Bs for the Satlink write chip address are"01010", while the bit Bi, is "0"The R/W bit, Bo, is"0"indicating a write (W). When the"P"bit (Bi) is a zero ("0"), the hexadecimal ("01010000") columns 94 and 96, translates to"50", column 98.

When the"P"bit is high or one ("1"), the hexadecimal ("01010100") columns 94 and 96, translates to"54" (in parentheses), column 98. The Satlink read chip address, row 95, shows the address used to indicate a read data/information to the 12C

bus/micro interface 40 of the Satlink section 30. The bits B7, B6, B5, B4, B3 for the Satlink read chip address are"01010", while the bit B1, is"0"The R/W bit, Bo, is"1" indicating a read (R). When the"P"bit (B1) is a zero ("0"), the hexadecimal ("01010001") columns 94 and 96, translates to"51", column 98. When the"P"bit is high or one ("1"), the hexadecimal ("01010101") columns 94 and 96, translates to"55" (in parentheses), column 98.

As well, the VSB/DCD write chip address, row 97, shows the address used to indicate a write data/information to the 12C bus/micro interface 42 of the VSB/DCD section 32/34. The bits B7, B6, B5, B4, B3 for the VSB/DCD write chip address are "01010", while the bit B1, is"1"The R/W bit, Bo, is"0"indicating a write (W). When the"P"bit (Bi) is a zero ("0"), the hexadecimal ("01010010"), columns 94 and 96, translate to the full address of"52", column 98. When the"P"bit is high or one ("1"), the hexadecimal ("01010110"), columns 94 and 96, translates to the full address of "56" (in parentheses), column 98. The VSB/DCD read chip address, row 99, shows the address used to indicate a read data/information to the 12C bus/micro interface 42 of the VSB/DCD section 32/34. The bits B7, B6, B5, B4, B3 for the VSB/DCD read chip address are"01010", while the bit B1, is"1"The R/W bit, Bo, is"1"indicating a read (R). When the"P"bit (Bi) is a zero ("0"), the hexadecimal ("01010011"), columns 94 and 96, translates to the full address of"53", column 98. When the"P"bit is high or one ("1"), the hexadecimal ("01010111"), columns 94 and 96, translates to"57" (in parentheses), column 98.

Referring now to Fig. 3, the integrated circuitry of the various sections may also be thought of in terms of blocks of integrated circuits. As such, these blocks may be merged onto the same IC substrate or chip to produce a single IC. The UL

IC 20UL integrates first and second slave devices 40 and 42 (i. e. the 12C bus/micro interfaces) which is representative of any type of 12C integrated IC. In this case, the first and second devices may comprise respective first and second sections of a single IC. As well, the 12C devices may be separate.

In Fig. 3, the I/0 pin 60 is shown connected to other circuitry/logic via line 72.

The other circuitry/logic 72 is representative of the generation of a control signal by software or other logic such that the addresses of the 12C slaves #1 and #2, change in accordance with the principles presented above. The generation of the control signal may take many forms.

While this invention has been described as having a preferred design and/or configuration, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.