INTERCONNECTION STRUCTURE OF HIGH-DENSITY THREE-DIMENSIONAL STACKED MEMORY, AND PREPARATION METHOD

WIPO Patent Application WO/2024/131211

A1

Disclosed in the present invention are an interconnection structure of a high-density three-dimensional stacked memory, and a preparation method, which relate to an integrated circuit technique, in particular to a three-dimensional semiconductor memory technique. The interconnection structure of a high-density three-dimensional stacked memory in the present invention comprises a three-dimensional storage structure body, which is formed by stacking conductive layers and insulating layers in a staggered mode, and a lead-out structure, wherein a contact face between the lead-out structure and an etched vertical face of the three-dimensional storage structure body has a stepped edge line, and the etched vertical face is a plane where a side face of the three-dimensional storage structure body, that is generated by means of etching and is perpendicular to a bottom face thereof, is located. The chip area occupied by the configuration wiring using the technique of the present invention is obviously smaller than that in the prior art, and the series resistance of a horizontal electrode is also greatly reduced.

PENG, Jack Zezhong (Floor 11 Unit 1, Building5, No.399, West Of Fucheng Road, Hi-tech Distric, Chengdu Sichuan 1, CN)
WANG, Ke (Floor 11 Unit 1, Building5, No.399, West Of Fucheng Road, Hi-tech Distric, Chengdu Sichuan 1, CN)

PCT/CN2023/123546

June 27, 2024

October 09, 2023

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CHENGDU PBM TECHNOLOGY LTD (Floor 11 Unit 1, Building5, No.399, West Of Fucheng Road, Hi-tech Distric, Chengdu Sichuan 1, CN)

H10B41/50

BEIJING FINELAND IP FIRM (11 Floor No.8 Caihefang Roa, Haidian District Beijing 0, CN)

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