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Patent Searching and Data


Title:
INTERRUPT CONTROLLER FOR A MICROPROCESSOR
Document Type and Number:
WIPO Patent Application WO2002050672
Kind Code:
A3
Abstract:
An interrupt controller for a microprocessor (30) having a plurality of event memories (40, 41) which are combined to form at least one group and each have an input for a setting signal (5) and an output for an event memory signal (4), where the microprocessor (30) has read and write access to the event memory signals (4) via a data bus (10), and where the event memories (40, 41) each have an input for a resetting signal (3), is designed such that the event memories can be specifically altered individually or else in groups without events being unintentionally lost in the process. To this end, the resetting signal (3) for an event memory (40, 41) in a group becomes active when the microprocessor (30) effects write access to the group containing this event memory (40, 41) using a first write signal (15) and, at the same time, that individual signal (16) from the microprocessor (30) which is associated with this event memory (40, 41) is active on the data bus (10).

Inventors:
BRUNHEIM RUEDIGER (DE)
Application Number:
PCT/EP2001/014611
Publication Date:
February 12, 2004
Filing Date:
December 12, 2001
Export Citation:
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Assignee:
THOMSON LICENSING SA (FR)
BRUNHEIM RUEDIGER (DE)
International Classes:
G06F9/48; (IPC1-7): G06F9/48; G06F9/46; G06F13/24; G06F13/26
Foreign References:
EP0443557A21991-08-28
EP0316138A21989-05-17
Other References:
PATENT ABSTRACTS OF JAPAN vol. 006, no. 192 (P - 145) 30 September 1982 (1982-09-30)
"METHOD OF IMPROVING PARALLEL PORT INTERRUPTS IN PERSONAL COMPUTERS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 35, no. 1A, 1 June 1992 (1992-06-01), pages 54 - 58, XP000308771, ISSN: 0018-8689
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