Title:
LEAD FRAME, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING LEAD FRAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/084483
Kind Code:
A1
Abstract:
[Problem] Even when using a mold resin having a low linear coefficient of expansion, to mitigate the occurrence of cracking in solder which is for joining a terminal section of a lead and a wiring substrate when a temperature changes. [Solution] A frame 1 according to an embodiment of the present invention is provided with: a lead section 2 that has an inner lead 3 and an outer lead 4 which is connected to the inner lead 3; and a frame section 5 that supports the lead section 2. The inner lead 3 is provided with a terminal section 3a that has an opposing surface 3b that opposes a conductive pattern of the wiring substrate, and a rear surface 3c on the side opposite to the opposing surface 3b. At a peripheral edge portion of the terminal section 3a, the inner lead is provided with a solder thickness securing portion 6 where the opposing surface 3b is recessed towards the rear surface 3c side, the solder thickness securing portion being formed so as to be thinner than the central region of the opposing surface 3b. No recess is formed in the central region of the rear surface 3c, which is flat.
Inventors:
KAMIYAMA YOSHIHIRO (JP)
UMEDA SOICHIRO (JP)
UMEDA SOICHIRO (JP)
Application Number:
PCT/JP2015/078363
Publication Date:
June 02, 2016
Filing Date:
October 06, 2015
Export Citation:
Assignee:
SHINDENGEN ELECTRIC MFG (JP)
International Classes:
H01L23/50
Foreign References:
| JPH0311607A | 1991-01-18 | |||
| JPH029158A | 1990-01-12 |
Other References:
See also references of EP 3226292A4
Attorney, Agent or Firm:
KATSUNUMA Hirohito et al. (JP)
Katsunuma Hirohito (JP)
Katsunuma Hirohito (JP)
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