Title:
LOW LATENCY FREQUENCY SWITCHING
Document Type and Number:
WIPO Patent Application WO2004040787
Kind Code:
A3
Abstract:
Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller (510) receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer (520). In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control (540) and gain control (530) are iterated to perform gain calibration, with signaling to control the iterations without need for processor (550) intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.
Inventors:
SHIU DA-SHAN
ZHANG LI
SY EUGENE
MALDONADO DAVID
DHALIWAL UPKAR
ZHANG LI
SY EUGENE
MALDONADO DAVID
DHALIWAL UPKAR
Application Number:
PCT/US2003/034784
Publication Date:
August 26, 2004
Filing Date:
October 31, 2003
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H03G3/30; (IPC1-7): H04B1/40; H04B1/30; H03D3/00
Foreign References:
| US6088343A | 2000-07-11 | |||
| EP1213830A1 | 2002-06-12 | |||
| CA2360266A1 | 2002-04-30 | |||
| US6459889B1 | 2002-10-01 | |||
| EP1172928A2 | 2002-01-16 | |||
| EP1102413A2 | 2001-05-23 |
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