Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/238282
Kind Code:
A1
Abstract:
A semiconductor device obtained by a manufacturing method according to the present disclosure has a multilayer wiring in which wiring layers and insulating layers are alternately stacked, the wiring layers adjacent to each other in the stacking direction, with the insulating layer interposed therebetween, being electrically connected to each other by a conductor present in a through hole provided in the insulating layer. The multilayer wiring is formed by providing the insulating layer having a metal protective film on the surface and including an inorganic filler having an average maximum particle length B of 1-100 μm on a substrate, forming the through hole in the insulating layer, and dry desmearing the insulating layer in which the through hole has been formed.
Inventors:
NISHIDO KEISUKE (JP)
TAKEKOSHI MASAAKI (JP)
TAKEKOSHI MASAAKI (JP)
Application Number:
PCT/JP2022/023129
Publication Date:
December 14, 2023
Filing Date:
June 08, 2022
Export Citation:
Assignee:
RESONAC CORP (JP)
International Classes:
H01L23/12
Foreign References:
| JP2003282773A | 2003-10-03 | |||
| JP2004235202A | 2004-08-19 | |||
| JP2017216398A | 2017-12-07 | |||
| JP2001119125A | 2001-04-27 | |||
| JPH104271A | 1998-01-06 |
Attorney, Agent or Firm:
TAIYO, NAKAJIMA & KATO (JP)
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