Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/073765
Kind Code:
A1
Abstract:
The present invention forms a dynamic flash memory, and has: a step for laminating a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P layer substrate 11; a step for forming a first hole penetrating through the stated layers on the P layer substrate 11; a step for filling the first hole and forming a semiconductor column 22; a step for removing the first and second material layers and forming second and third holes; a step for oxidizing the surface layer of the semiconductor column 22 exposed in the second and third holes and forming first gate insulating layers 25a, 25b; and a step for filling the second and third holes and forming first and second gate conductor layers 26aa, 26ba.
Inventors:
SHIROTA RIICHIRO (TW)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2021/039319
Publication Date:
May 04, 2023
Filing Date:
October 25, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SHIROTA RIICHIRO (TW)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
SHIROTA RIICHIRO (TW)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
H01L21/8234; H01L21/336; H01L27/088; H01L27/10; H01L29/78
Foreign References:
| JP2003086712A | 2003-03-20 | |||
| JP2012015517A | 2012-01-19 | |||
| JP2009026448A | 2009-02-05 | |||
| JP2000340679A | 2000-12-08 | |||
| JP2003188279A | 2003-07-04 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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