Title:
METHOD FOR PERFORMING BNN OPERATION THROUGH IN-MEMORY COMPUTING USING DRAM, AND DEVICE USING SAME
Document Type and Number:
WIPO Patent Application WO/2023/022505
Kind Code:
A1
Abstract:
Disclosed are: a dynamic random access memory (DRAM) operator which performs a binary neural network (BNN) operation through in-memory computing; and a method for performing a BNN operation through in-memory computing. The DRAM operator comprises: DRAM including a plurality of MATs including a cell array including a plurality of cells arranged on a plurality of bit lines and a plurality of word lines; a comparator in which (i) a first input terminal is connected to at least one first bit line including a plurality of first cells through a first comparator switch, and (ii) a second input terminal is connected to at least one second bit line including a plurality of second cells through a second comparator switch, and which outputs a first binary output value or a second binary output value as a BNN operation value by comparing first bit line voltage of the first bit line with second bit line voltage of the second bit line, wherein the first bit line may be located in the same MAT or a different MAT as the second bit line; and an in-memory computing control unit which saves weight bit data to the first cells or the second cells by applying word line voltage to the word lines according to a writing signal from the DRAM and applying cell charging voltage to the first bit line or the second bit line, applies the word line voltage to the word lines according to a BNN input value in response to an operation signal in a state in which the first bit line and the second bit line are pre-charged, and turns on the first comparator switch and the second comparator switch so that the comparator outputs the first binary output value or the second binary output value, wherein each of BNN weights used in the BNN operation is represented by specific first weight bit data and specific second weight bit data.
Inventors:
CHO SEONG HWAN (KR)
YOON HYE IN (KR)
YOON HYE IN (KR)
Application Number:
PCT/KR2022/012270
Publication Date:
February 23, 2023
Filing Date:
August 17, 2022
Export Citation:
Assignee:
KOREA ADVANCED INST SCI & TECH (KR)
International Classes:
G06N3/063; G11C11/408; G11C11/4091; G11C11/4094
Other References:
SHIN HYEIN; SIM JAEHYEONG; LEE DAEWOONG; KIM LEE-SUP: "A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks", 2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), IEEE, 4 November 2019 (2019-11-04), pages 1 - 8, XP033678137
JIANG LEI; KIM MINJE; WEN WUJIE; WANG DANGHUI: "XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs", 2017 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), IEEE, 24 July 2017 (2017-07-24), pages 1 - 6, XP033142397, DOI: 10.1109/ISLPED.2017.8009163
ALONSO DAVID ATIENZA, QIU QINRU, REDA SHERIEF, CHEN YIRAN, GUPTA SARANSH, IMANI MOHSEN, ZHAO HENGYU, WU FAN, ZHAO JISHEN, ROSING T: "Implementing binary neural networks in memory with approximate accumulation", PROCEEDINGS OF THE ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISPLED '20, BOSTON MASSACHUSETTS, ACM, NEW YORK, NY, USA, vol. 20, 10 August 2020 (2020-08-10), New York, NY, USA, pages 247 - 252, XP093037644, ISBN: 978-1-4503-7053-0, DOI: 10.1145/3370748.3406562
LI SHUANGCHEN; NIU DIMIN; MALLADI KRISHNA T.; ZHENG HONGZHONG; BRENNAN BOB; XIE YUAN: "DRISA: A DRAM-based Reconfigurable In-Situ Accelerator", 2017 50TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), ACM, 14 October 2017 (2017-10-14), pages 288 - 301, XP033536724
LEE CHAEUN: "Design and Optimization for Energy Efficient and Variation Resilient RRAM-based Neural Networks", M.S. THESIS, DESIGN AND OPTIMIZATION FOR ENERGY EFFICIENT AND VARIATION RESILIENT RRAM-BASED NEURAL NETWORKS, 1 February 2020 (2020-02-01), XP093037642
JIANG LEI; KIM MINJE; WEN WUJIE; WANG DANGHUI: "XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs", 2017 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), IEEE, 24 July 2017 (2017-07-24), pages 1 - 6, XP033142397, DOI: 10.1109/ISLPED.2017.8009163
ALONSO DAVID ATIENZA, QIU QINRU, REDA SHERIEF, CHEN YIRAN, GUPTA SARANSH, IMANI MOHSEN, ZHAO HENGYU, WU FAN, ZHAO JISHEN, ROSING T: "Implementing binary neural networks in memory with approximate accumulation", PROCEEDINGS OF THE ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISPLED '20, BOSTON MASSACHUSETTS, ACM, NEW YORK, NY, USA, vol. 20, 10 August 2020 (2020-08-10), New York, NY, USA, pages 247 - 252, XP093037644, ISBN: 978-1-4503-7053-0, DOI: 10.1145/3370748.3406562
LI SHUANGCHEN; NIU DIMIN; MALLADI KRISHNA T.; ZHENG HONGZHONG; BRENNAN BOB; XIE YUAN: "DRISA: A DRAM-based Reconfigurable In-Situ Accelerator", 2017 50TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), ACM, 14 October 2017 (2017-10-14), pages 288 - 301, XP033536724
LEE CHAEUN: "Design and Optimization for Energy Efficient and Variation Resilient RRAM-based Neural Networks", M.S. THESIS, DESIGN AND OPTIMIZATION FOR ENERGY EFFICIENT AND VARIATION RESILIENT RRAM-BASED NEURAL NETWORKS, 1 February 2020 (2020-02-01), XP093037642
Attorney, Agent or Firm:
SU INTELLECTUAL PROPERTY (KR)
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