Title:
METHOD FOR PRODUCING MULTILAYER CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2023/127470
Kind Code:
A1
Abstract:
The present invention provides a method for producing a multilayer ceramic capacitor which comprises: a capacitor main body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked; a first via conductor which is arranged within the capacitor main body and is electrically connected to the plurality of first internal electrodes; a second via conductor which is arranged within the capacitor main body and is electrically connected to the plurality of second internal electrodes; a first external electrode which is arranged on the surface of the capacitor main body and is electrically connected to the first via conductor; and a second external electrode which is arranged on the surface of the capacitor main body and is electrically connected to the second via conductor. This method for producing a multilayer ceramic capacitor comprises: a step (S1) in which a conductive paste for internal electrodes and a conductive paste for dummy electrodes are applied to a ceramic green sheet; a step (S2) in which a mother multilayer body is produced by stacking a plurality of ceramic green sheets, to each of which the conductive paste for internal electrodes and the conductive paste for dummy electrodes have been applied; a step (S3) in which a plurality of through holes that extend in the stacking direction of the ceramic green sheets are formed in the mother multilayer body, and the thus-formed plurality of through holes are filled with a conductive paste for via conductors; a step (S5) in which the mother multilayer body, which has been filled with the conductive paste for via conductors, is cut at positions, where the conductive paste for internal electrodes is not applied, in the stacking direction, thereby being separated into a plurality of individualized unburned chips; a step (S9) in which an unburned chip is burned, thereby obtaining a capacitor main body; and a step (S10) in which a first external electrode and a second external electrode are formed on the capacitor main body. The step (S5) for individualizing a plurality of unburned chips comprises a process for cutting the mother multilayer body at positions where the conductive paste for dummy electrodes is applied.
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Inventors:
IZUMI YOSHIHIKO (JP)
FUJITA YUKIHIRO (JP)
FUJITA YUKIHIRO (JP)
Application Number:
PCT/JP2022/045622
Publication Date:
July 06, 2023
Filing Date:
December 12, 2022
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30
Foreign References:
| JP2007096265A | 2007-04-12 | |||
| JP2021048261A | 2021-03-25 | |||
| JP2011228390A | 2011-11-10 | |||
| JP2007173775A | 2007-07-05 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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