Title:
METHODS FOR FORMING DIELECTRIC LAYER IN FORMING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/028921
Kind Code:
A1
Abstract:
Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.
Inventors:
YANG YONGGANG (CN)
ZHOU XIAOHONG (CN)
ZHOU XIAOHONG (CN)
Application Number:
PCT/CN2021/115993
Publication Date:
March 09, 2023
Filing Date:
September 01, 2021
Export Citation:
Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
H01L27/11551; H01L27/11582; H01L27/11575
Foreign References:
| CN107564916A | 2018-01-09 | |||
| CN109817521A | 2019-05-28 | |||
| CN109065545A | 2018-12-21 | |||
| TW202044343A | 2020-12-01 | |||
| TW325581B | 1998-01-21 | |||
| US6117798A | 2000-09-12 | |||
| CN105719964A | 2016-06-29 |
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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