Title:
MULTILAYER CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2023/176538
Kind Code:
A1
Abstract:
This multilayer ceramic capacitor includes a capacitor body 1 in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked, first via conductors 5 provided inside the capacitor body 1 and electrically connected to the plurality of first internal electrodes, second via conductors 6 provided inside the capacitor body 1 and electrically connected to the plurality of second internal electrodes, a first external electrode provided on the surface of the capacitor body 1 and electrically connected to the first via conductors 5, and a second external electrode provided on the surface of the capacitor body 1 and electrically connected to the second via conductors 6. When the capacitor body 1 is viewed in the stacking direction of the dielectric layers, the first internal electrodes, and the second internal electrodes, with respect to a reference arrangement in which m × n (m and n are natural numbers of 3 or more) virtual lattice points are set and the via conductors including the first via conductors 5 and the second via conductors 6 are arranged at all virtual lattice points, the first via conductors 5 and the second via conductors 6 are not arranged at the number of virtual lattice points of 1 or more and (m - 2) × (n - 2) or less that are located on the inside with respect to the virtual lattice points located on the outermost periphery.
Inventors:
KAKOMURA KENGO (JP)
FUJITA YUKIHIRO (JP)
HIDAKA SEIJI (JP)
FUJITA YUKIHIRO (JP)
HIDAKA SEIJI (JP)
Application Number:
PCT/JP2023/008255
Publication Date:
September 21, 2023
Filing Date:
March 06, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30
Foreign References:
| JPH11204372A | 1999-07-30 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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