OPTIMIZATION OF DIE PLACEMENT ON WAFERS

Title:

OPTIMIZATION OF DIE PLACEMENT ON WAFERS

Document Type and Number:

WIPO Patent Application WO2003096234

Kind Code:

A3

Abstract:

A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion (21); inputting opptimization data (23), performing optimization (22, 24, 25, 26, 27, 28) to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data (23).

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Inventors:

CADOURI EITAN

Application Number:

PCT/US2003/014613

Publication Date:

February 12, 2004

Filing Date:

May 12, 2003

Export Citation:

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Assignee:

PDF SOLUTIONS INC (US)

International Classes:

G03F7/20; H01L21/66; (IPC1-7): G06F17/50; G06F19/00

Foreign References:

US20020123818A1	2002-09-05
US6070004A	2000-05-30
US6393602B1	2002-05-21
US5498579A	1996-03-12
US6341241B1	2002-01-22

Other References:

SARMA K. ET AL.: "Wafer level reliability application to manufacturing of high performance microprocessor", IEEE INTERNATIONAL RELIABILITY WORKSHOP, 20 October 1996 (1996-10-20), pages 77 - 81, XP010219573
GASSER R.A.: "Yield learning and volume manufacturing of high performance logic technologies on 200mm and 300mm wafers", INTERNATIONAL ELECTRON DEVICES MEETING, 2 December 2001 (2001-12-02), pages 28.1.1 - 28.1.4, XP010575197

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