PHOTO-VOLTAIC DEVICE

FIELD OF THE INVENTION

The present invention relates to photovoltaic devices and methods.

The invention has been developed primarily for use in photovoltaic systems and will be described hereinafter with reference to this application. However, it will be appreciated that the invention is not limited to this particular field of use.

BACKGROUND OF THE INVENTION

Any discussion of the prior art throughout the specification should in no way be considered as an admission that such prior art is widely known or forms part of the common general knowledge in the field.

As the world's awareness of environmental issues becomes more intense, alternate forms of energy to fossil fuels are being sought and renewable sources of energy such as solar energy have increasing importance and commercial value. As a result, considerable effort is being invested in the development of Photovoltaic (PV) cells which convert sunlight directly into electricity.

PV cells generally fall into one of three classes:

1. Conventional bulk-semiconductor cells made from multi-crystalline or polycrystalline silicon ;

2. Thin film cells made from materials such as silicon or Copper Indium Gallium Selenide (CIGS) deposited on glass or other low cost substrates, and

3. Concentrator cells which are made using sophisticated epitaxial semiconductor structures to achieve superior energy conversion efficiency.

Conventional bulk-semiconductor solar cells have been the focus of much of the world's attention for many decades. The proven performance of these silicon structures and their relatively low cost, due to the abundance of silicon as a raw material and simple processing procedures, has made this the solar technology of choice for many terrestrial applications. Despite the considerable investment that has been made into this technology, the conversion efficiency of these silicon cells has reached a commercially practical limit of around 22%. This limit is not an issue in many "consumer grade" installations and this technology continues to flourish. The cost per watt of electricity generated from these conventional cells is currently around $2 - $3 (USD).

Thin film PV cells are a relatively recent development and are intended to reduce the cost per watt generated of PV installations. Conventional silicon PV cells are made on substrates which have high purity and regular atomic lattice structure. Although these substrates benefit from the silicon semiconductor industry's volumes and price points, the need to have the entire substrate made from high quality material is a significant cost burden. As the name suggests, thin film cells are made by depositing only a thin layer of semiconductor material on low cost substrates such as glass, stainless steel or plastic. Although the use of these substrate materials reduces the amount of semiconductor material needed dramatically (e.g. maybe by a factor of 100), it makes the task of forming defect free crystal structures much more difficult because the thin film layer does not have a uniform crystal template to align to during growth. The relatively poor semiconductor quality of these structures results in conversion efficiencies of barely 10%. Despite this, the cost per watt of thin film installations is generally less than $2 per watt. This means that thin film cells are becoming increasingly popular, even though the poor efficiency means more than twice as much collecting area is needed (compared to bulk silicon cells) per watt generated.

High performance Concentrator Photo- Voltaic (CPV) technologies are the most recent PV innovation. The concept of using low cost optical elements to collect and focus light onto relatively small cells has been known for many years. Using this approach, not only can the semiconductor proportion of an installation's cost be reduced, but a more exotic semiconductor structure can be employed to provide higher conversion efficiencies. Much of the innovation occurring at the present time relates to the design of sophisticated epitaxial structures that increase cell efficiency. These structures generally employ compound semiconductors made from elements such as aluminium, gallium, indium, arsenic, phosphorous and other related elements in groups III and V of the periodic table. The structures are typically grown on high purity, mono-crystalline substrates made from germanium or gallium arsenide. In making these cells, it is common to use a so-called "multi-junction" structure where several different cells are stacked one on top of the other. For example, the top cell in such a multi-junction structure might be made from indium gallium phosphide (InGaP), the middle cell might be made from gallium arsenide (GaAs) and the bottom cell might be made from germanium (as a result of using germanium as the substrate for crystal growth). The top cell converts short wavelength solar radiation to electric current but transparently passes longer wavelengths through to the lower cells. These cells also convert a portion of the solar spectrum to electric current according to the bandgap of the materials used. In being stacked together, the outputs of the individual cells are combined in series to raise the voltage (and hence power) generated from the cell. The key advantage of these multijunction devices over other single junction semiconductor structures is that they convert sunlight into electricity more efficiently. This is achieved by tailoring the semiconductor structure to absorb light in relatively narrow spectral bands. This means that different layers in the cell convert "blue", "green" and "red" portions of the incoming spectrum separately. The terms "blue", "green" and "red" are used here to describe relative portions of the solar spectrum and should not be taken literally. This multijunction approach results in better quantum efficiencies and less waste heat generation from carrier thermalisation in the cell.

The current world record for energy conversion of this type of cell is around 41%, double that of the best conventional bulk silicon-based technologies. Although these semiconductor structures are more complex and costly to produce, this has relatively little impact on CPV systems because the semiconductor area needed is only a small fraction of the optical collecting area. Typically, CPV systems use lenses or mirrors as the primary optical concentrating elements to provide concentration ratios of around 500 times. Therefore, although the cost of the multi-junction cell might be 100 times higher than silicon per unit area, the semiconductor area needed can be reduced by 500 (or more) thereby reducing the semiconductor component of system costs by at least a factor of 5. At the same time, these cells generate twice as much energy per unit area as a result of their higher intrinsic efficiencies. This cost advantage is so substantial that it is predicted that the cost per watt of CPV installation will be lower than thin film technologies, despite the fact that installations need to use mechanical tracking systems to keep cells and associated optical elements pointed at the sun. - A -

Additional features of these conventional CPV systems will now be discussed in the following paragraphs.

In the context of the present invention multijunction cell development is discussed.

Multijunction cells were initially developed for satellite power supply systems and have been used in this market for a number of years. The nature of this application demands the highest possible efficiency and lowest launch weight. The cost of satellite PV systems is generally a secondary consideration and PV cells for space applications are sold at a considerable premium. The resulting mindset seems to have influenced current cell and module designs. In particular, modules presently lack the engineering refinement needed to be successful in the high volume, cost-sensitive terrestrial CPV market.

Evidence of the early developmental state of the current terrestrial CPV technologies can be seen in the slowly evolving set of performance, qualification and safety standards relating to CPV installations. Although basic standards exist in the form of IEEE 1513 and IEC 62108 specifications, these standards still do not adequately address performance rating, tracking characteristics and safety issues.

As noted above, conventional CPV subsystems typically use lenses or mirrors as the primary optical concentrating elements. Two prior art examples will now be discussed.

US patent 5118361 filed 21 May 1990 by Fraas et al and assigned to The Boeing Company describes a CPV array using Fresnel lenses as the primary concentrating element. The content of this patent is included herein by reference. The patent describes the structure and manufacturing method of a CPV module and panel. FIG. 1 provides an overview of the design described in this patent including overall panel housing 100, cell module assemblies 101 and Fresnel lenses 102. hi this type of system, sunlight is concentrated approximately 500 times by the Fresnel lens and focused directly on the multijunction PV cell.

The disclosure and claims of this patent relate to the use of metallised flexible circuit "tapes" which have apertures distributed along their length in which cells are mounted, hi this design, as shown in FIG. 2, cell substrates 201 are bonded directly to electrical conductors 203 formed on the surface of the flexible tape 200. After bonding, the cell and tape assembly is glued to panel heat spreaders at points along its length where cells are located. Since the flexible circuit tape allows a degree of movement along the assembly, the cells can be optically aligned within each subsystem before the bonding agent sets thereby fixing them permanently to the rigid heat spreader.

Several drawbacks of this design have been identified. Firstly, when fragile cells are bonded to a flexible structure (i.e. the "tape"), physical movement of the tape couples mechanical stress onto the cells and there is a chance that cell contacts, cell metallisation or cell substrates can be damaged. This risk exists until the cell string is bonded to a portion of the panel housing which is relatively late in the overall assembly process. This patent therefore presents a design which is not physically robust and which presents difficulties in shipping and handling cell assemblies prior to panel assembly. Secondly, the proposed design produces a string of cells that are fundamentally interconnected as a single structure. This means that there is no way of easily replacing a failed cell module after manufacture or after panel assembly particularly since cells are glued to heat spreading assemblies. Therefore this patent does not present a design which allows modular replacement of faulty cells. Thirdly, because the proposed design uses laminated circuit structures (tapes) to interconnect cells, the cost of the system is increased compared to conventional wiring interconnection. Therefore the patent presents a design with added costs. Fourthly, the manufacturing process used to assemble the cells and flexible circuit tape does not use industry standard techniques suited to high volume, low cost manufacturing. Therefore the patent does not present a design that can be produced in volume at low cost. Fifthly the proposed design does not address the need to prevent environmental degradation of the cell module performance due to, for example, moisture ingress. The design also does not address the need for operational maintenance such as cleaning. The patent therefore does not propose a design that is suited to harsh operating environments. Finally, the design does not address issues relating to high voltage isolation of the cell and its connections from the associated heatsink and panel housing. The patent therefore does not present a design that addresses high voltage operational safety.

US patent application 2006/0266408 filed by Home et al on 26 May 2005 describes a CPV module made using a cassegrain optical concentrator. The content of this patent application is also included herein by reference. FIG. 3 a shows the elements of the design including the overall cassegrain assembly 300a, primary focusing mirror 301a, secondary focusing mirror 302a and cell module assembly 303 a. FIG. 3b provides a side view of these same elements. Multijunction cell 304b is located inside cell module assembly 303b. In this design, sunlight is focused by the primary mirror onto the secondary mirror and then onto the PV cell. The advantage of this design is that the optical path is folded so that the vertical dimension of the optical system 305b is reduced and therefore the CPV panel can be reduced in thickness and in cost. The disadvantage of this design is that the secondary reflector 302 creates a shadow on the primary reflector and reflects light away from the cell. This shadowing loss is typically around 3%.

The proposed design addresses the need for modularity of the cell assembly by describing a structure and manufacturing process that results in a well defined compact module. The design also makes use of standard wiring for cell module interconnection to achieve the lowest possible interconnection cost. However, several fundamental flaws have been identified in this design. Firstly, the proposed design relies on the assembly of small customised piece-parts and non-industry standard assembly processes. The patent application therefore describes a module which is labour-intensive to make and which is not well suited to high volume, low cost manufacturing processes. Secondly, the proposed design does not address details relating to careful management of the thermal coupling between cell and panel housing to ensure lowest possible cell operating temperatures. Therefore the patent application does not present a design which carefully and reproducibly controls cell operating temperature. Thirdly, although mounting of optical elements of the design is mechanically robust and well described, the mechanical securing of the heavy gauge interconnect wires to the cell assembly is not addressed. Without such securing, the cell module design is potentially able to be damaged by mechanical forces applied to the interconnect wires during shipping, installation or maintenance. The design presented in the patent application therefore does not provide a mechanically robust interconnection scheme. Fourthly, the proposed design does not provide any degree of environmental sealing to prevent, for example, moisture ingress into the cell module. The mechanical assembly is designed to quickly snap together and allows disassembly. This means that the surface of the cell and adjacent connections are not sealed and are exposed to environmental influences such as condensation or corrosion. The proposed design therefore does not provide a cell module suited to harsh operating conditions. Fifthly, because the proposed design relies on mechanical spring force to press the optical guiding element onto the surface of the cell, it is possible that a small air gap can exist at the interface which will reflect a percentage of incoming light out of the system, thereby decreasing efficiency. The design presented in the patent application therefore does not ensure reliable optical coupling to the cell. Finally, the proposed design does not address the need for high voltage isolation between the cell contacts and the adjacent grounded panel housing, metallised optical elements or cell module casing. The proposed design therefore does not address the need for high voltage operational safety.

Currently, many CPV system suppliers employ ad-hoc assembly practices in order to get solar panels and associated tracking systems to market quickly. Presently many companies are highly vertically integrated, undertaking panel and tracker design as well as cell module design. It is therefore common for system manufacturers to buy unpackaged cells and use proprietary assembly procedures to produce CPV modules and panel assemblies. Often, these systems integrators use assembly techniques which are incompatible with low cost, volume manufacturing processes. There is a substantial need for a new module design and manufacturing method which is suited to low cost, high volume standard manufacturing processes.

There has been relatively little development in the area of low cost CPV cell module design. US patent 5460659 filed by Krut on 10 December 1993 and assigned to Spectrolab Inc proposes the use of standard integrated circuit packages to solve the cell packaging problem. The content of this patent is also included herein by reference. This patent relates to so-called CPV microarrays where cell and concentrating optic dimensions are reduced by a factor of approximately 10. The advantage of microarrays is that panel thickness can be reduced significantly. The patent describes arrays of cells mounted in standard integrated circuit packages and assembled onto panel-sized circuit boards. FIG. 4 provides an overview of the proposed structure including cell module 400, standard integrated circuit package 401, CPV cell 402 and optical element 403.

The design disclosed in this patent has a number of serious flaws. Firstly, in CPV systems where optical concentration ratios are for example 500, the design proposed in the '659 patent uses 500 times as much PCB area as cell area, i.e. it is wasteful in its use of PCB material. Secondly, the design disclosed in the patent does not address the significant issue of thermal management of the cells which is made more difficult given the proposed packaging solution. Thirdly, the design does not give any consideration to the significant problem of high voltage isolation between the cell module and system grounding. Fourthly, the proposed design does not give any consideration to sealing the cell and associated components from environmental influences such as humidity, condensation, airborne pollutants or corrosive substances. Finally, the optimum size for multijunction cells in current commercial subsystems is approximately 1 cm x 1 cm. There are relatively few standard IC packages which can accommodate chips this big and which match the requirements of CPV applications. Those that maybe suitable are likely to be non standard and relatively costly.

Commercial products offered in the current CPV market have similar deficiencies that prevent them from providing an attractive embodiment for cost sensitive CPV applications.

FIG. 5 provides a diagrammatic view of a CPV module currently produced by Spectrolab Inc. This module 500 is comprised of an insulating substrate 501 with a patterned metallic surface 502 onto which a multijunction cell 503 is mounted. Wires 504 are used to provide module interconnection. The module also includes a discrete bypass diode 506 to protect the cell in overload conditions. Each of the components and connections are bonded to the metallic surface of the insulating substrate 502 using fillets of solder or conductive adhesive.

FIG. 6 shows a similar CPV module marketed by Emcore Corporation. Substrate 601 is made from metal with a second insulating substrate 602 bonded to the surface. Cell 603 is connected to metal features on the surface of substrate 602 using busbars 608 that are connected to the cell 603 by soldering, braising or welding. Bypass diode 606 is also bonded to the surface of substrate 602. Large metallic terminals 607 are bonded to the surface of substrates 601 and 602 to provide means of connecting the module in a subsystem.

The key advantage of the designs shown in FIGs 5 and 6 is that they provide excellent thermal characteristics. The back surface of the cell in each case is intimately bonded to a substrate which has high thermal conductivity and which can convey waste heat out of the cell efficiently. These substrate are made from materials such as aluminium nitride and controlled thermal expansion copper alloys.

Although these materials provide excellent thermal characteristics, they generally require that the cell modules built on them are assembled one at a time using non- standard, proprietary assembly processes that do not make use of low cost, high volume techniques. Secondly, the module designs of FIGs 5 and 6 do not provide any mechanical protection for the cells which are made from fragile material that is easily damaged. This is an issue in shipping modules and handling them during installation and maintenance. Neither module addresses the operational necessity of cleaning the surface of the cell from time to time to remove dust or pollutants. The designs are not mechanically robust and are not well suited to being handled and cleaned. Thirdly, the designs do not provide any features that provide high voltage isolation. In a typical CPV panel, many cell modules are connected in series. This means that the terminals of the cells at the high potential end of the series connection are at least several hundred volts above ground potential. The substrate designs of the modules 500 and 600 provide excellent thermal characteristics by coupling heat through to the subsystem housing. This implies that on one side these substrates are in intimate contact with the subsystem housing which is maintained at ground potential for safety reasons. On the other side, these substrates have terminals that are at a considerable DC potential. Given the DC nature of cell arrays, if a breakdown event occurs across this insulating barrier, a DC arc will form that represents a significant fire hazard.

From another perspective, if the CPV panel needs to be monitored in operation, the exposed terminal structure of the designs represents a significant safety hazard for maintenance personnel. In general, installations generating as much power as produced by CPV panels require substantial degrees of electrical insulation to safeguard personnel. Emerging standards in the PV area suggest that panel wiring and modules need to provide insulation between cell terminals and ground that can withstand several thousand volts. The module designs in FIGs 5 and 6 do not address this need in any way. Although there has been considerable development in the area of epitaxial structures for multijunction photovoltaic cells, there has been relatively little development of metallisation techniques for applying contacts to the cells. The challenges in designing metallisation structures relate to forming low resistance contacts to both the front (i.e. the photoactive side) of the multijunction cell and the back of the cell substrate and to patterning the front metallisation so as to shadow as little of the active area as possible.

FIG. 14 shows a structure of a prior art multijunction cell 1400 (not to scale). The cell structure comprises a substrate 1401 which is typically germanium and a multijunction epitaxial structure 1402 which performs the optical to electrical energy conversion function. The surface of the multijunction cell 1403 is optically transparent and allows light to enter the cell structure below. Metallic fingers 1407 are deposited on the active surface of the cell to provide electrical contact. These fingers need to carry the operating current of the cell and hence are made from relatively thick metal. For example, these fingers maybe 10 microns thick.

In order for these contact fingers to make stable, low resistance ohmic contacts with the semiconductor structure beneath them, a multilayer contact structure is used. In this structure, a low bandgap semiconductor layer 1404 is grown on the surface of the multijunction cell structure. The bandgap of this material is chosen to facilitate the formation of ohmic contacts with the surface. GaAs or LiGaAs has been used for this layer in prior art devices. Before the contact finger metal 1407 is deposited, an alloying metal layer 1405 is deposited on the surface of ohmic contact layer 1404. In prior art devices this alloying metal 1405 is a eutectic alloy of gold and germanium which melts at approximately 400 degrees Celsius. A diffusion barrier layer 1406 is deposited on top of this alloying metal layer to prevent contact metal 1407, which is typically gold or silver, from diffusing downwards into the cell structure. This diffusion barrier layer is generally nickel in prior art devices. An ohmic contact is formed when the overall structure is heated to approximately the melting temperature of the eutectic alloy. At this time the constituents of the alloy diffuse rapidly into the ohmic contact layer 1404 and produce an ohmic contact. Similarly, a second metal layer 1409 is deposited on the back of the wafer to provide the other contact to the cell. In prior art cells, if the substrate is made from germanium, a gold interface layer 1408 may be used to form an alloying contact in a similar fashion to the front contact. Alternatively, the back metal itself 109 can be gold.

US patent 5223043 filed on 11 May 1992 by Olson et al and assigned to the US Department of Energy discloses the use of electroplated Au for layers 1407 and 1409 without the use of other contacting layers.

US patent 6300558 filed on 20 April 2000 by Takamoto et al and assigned to Japan Energy Corporation discloses the use of AuGe / Ni / Au for layers 1405 / 1406 /1407 respectively and AuZn / Au for layers 1408 / 1409.

US patent 6600100 filed on 21 August 2001 by Ho et al and assigned to Emcore Corporation discloses the use of "metals predominantly including Ag" for both font and back contacts.

US patent 7115811 filed on 3 January 2003 by Ho et al and assigned to Emcore Corporation discloses the use of Ti / Au / Ag for layers 1405 / 1406 /1407 respectively.

US patent application 2006/0180198 filed on 10 February 2006 by Takamoto et al and assigned to Sharp Kabushiki Kaisha discloses the use of AuGe / Ni / Ag for layers 1405 / 1406 /1407 respectively with an additional thin layer of Au between layers 1406 and 1407. The patent also discloses the use of Au / Ag for layers 1408 / 1409.

The content of each of these patents is included herein by reference.

The inventor has realised that there are serious drawbacks with these known techniques of making contact to multijunction cells. Firstly, the use of precious metals such as gold and silver significantly increases cell costs, particularly since they need to be deposited in relatively thick layers.

Secondly, in order to deposit thick layers economically electroplating is generally preferred. The electroplating of metals such as gold requires the use of toxic compounds such as gold cyanide which represents a safety hazard for factory staff and which is not necessarily compatible with processing techniques used to make cells. Thirdly, the use of alloyed contacts on the photoactive (front) side of the cell results in manufacturing reproducibility. Gold and germanium diffuse rapidly into compound semiconductors such as GaAs and disrupt the crystal lattice in doing so. Therefore it is difficult to control the precise depth of the diffusion during manufacture and it is possible that the alloying process can diffuse too deep, damaging the multijunction cell structure. Furthermore, if cells are heated to elevated temperatures during operation the diffusion process will continue and will degrade cell performance.

Fourthly, although materials such as silver offer high electrical conductivity, they corrode or tarnish rapidly.

Finally, the thermal expansion coefficient of materials such as silver are significantly higher than GaAs or Ge and hence these materials can cause significant thermal stresses to epilayers and substrates.

Therefore, there is a need for a metallisation process for multijunction photovoltaic cells which uses low cost metals, which are safe and easy to deposit in thick layers, which do not rely on alloying to make ohmic contact with photoactive side cell layers and which have thermal expansion coefficients which are more closely matched to cell semiconductor materials.

From a different perspective, the inventor is aware that improvements are also needed in cell design which reduce shadowing of the photoactive surface of the cell by front side metallisation.

FIG 15 shows a multijunction cell 1500 marketed by Emcore Corporation. The cell comprises a peripheral busbar 1501 and contact fingers 1502 on the photoactive side of the cell. Busbar 1501 covers a considerable area of the cell (approximately 29%). This means that the semiconductor material underneath the busbar cannot be utilised and is represents a considerable waste of expensive cell material.

FIG. 16 shows a diagrammatic view of a multijunction cell 1600 marketed by Spectrolab Inc. This design also has busbars 1601 and contact fingers 1602, but the contact finger arrangement only requires busbars on two sides of the cell. This means that cell semiconductor material wastage is lower (approximately 10%). The inventor is aware of the considerable cost of multijunction cell structures and the significant commercial advantage that can be provided by increasing the utilisation of multijunction cell area. Accordingly there is a need for a multijunction cell structure that reduces shadowing of the cell surface and increases cell are utilisation, and hence lowers costs.

Certain features of prior art multijunction cells can now be discussed in the following paragraphs to establish the need for improvement and innovation.

US patent 7122733, filed by Narayanan et al on 6 September 2002, assigned to The Boeing Company and titled "Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds", includes a useful overview of the art of producing multi-junction solar cells. This patent is incorporated herein by reference, and provides the following summary:

"In a multiple cell device, semiconductive materials are typically lattice-matched to form multiple p-n (or n-p) junctions. Thep-n (or n-p) junctions can be of the homojunction or heterojunction type. When solar energy is received at a junction, minority carriers (i.e., electrons and holes) are generated in the conduction and valence bands of the semiconductor materials adjacent the junction. A voltage is thereby created across the junction and a current can be utilized therefrom. As the solar energy passes to the next junction, which can be optimized to a lower energy range, additional solar energy at this lower energy range can be converted into a useful current. With a greater number of junctions, there can be greater conversion efficiency and increased output voltage.

Whether in the multiple-junction or single-junction PV device, a conventional characteristic of PV cells has been the use of a single window layer disposed on an emitter layer which is disposed on a base layer. Further, the base layer may be disposed on a back surface field layer which is disposed on a substrate. The window layer and the back surface field layers are of higher bandgap semiconducting material lattice matched to the whole structure. The purpose of the top window layer and the back-surface field layer have been to serve both as a passivation layer and a reflection layer due to high electric fields associated with the high bandgap. The photo-generated carriers, such as the electrons in the 2009/001350

- 14 - emitter layer and the holes in the base layer, can further be reflected towards the p-n junction (which is the emitter and the base layer interface), for recombination and for generating electricity.

For a multiple-cell PV device, efficiency is limited by the requirement of low resistance interfaces between the individual cells to enable the generated current to flow from one cell to the next. Accordingly, in a monolithic structure, tunnel junctions have been used to minimize the blockage of current flow. In a multiple wafer structure, front and back metallization grids or contacts with low coverage fraction and transparent conductors have been used for low resistance connectivity. Since the output power is the product of voltage and current, a multi-junction solar cell can be designed with multiple junctions comprised of materials having different bandgaps, so that each junction can absorb a different part of the wide energy distribution of photons in sunlight. Additionally, uniform current generating characteristics may be produced.

Materials for a solar cell are conventionally grown epitaxially in a metal organic vapor phase epitaxy (MOVPE) system, also known as a metal organic chemical vapor deposition (MOCVD) system. During material growth, the lattice parameter for all of the different cell layers comprising the solar cell should be the same as that of the substrate. Ill— V compound materials of different compositions, but with the same lattice parameter as that of the substrate, are used to achieve different bandgaps that are typically required for multijunction solar cells. These layers are usually grown on a III— V substrate such as a GaAs wafer. In order to reduce the cost of the substrate material as well as to increase the over all power to weight ratio from the solar cell, a GaAs nucleated Ge substrate can be used. The lattice parameter of the Ge substrate is about 5.64613

Angstroms and that of GaAs is about 5.6533 A with little mismatch between the lattice parameters. Although the Ge atomic structure is of a diamond structure pattern and that of GaAs is of a zinc-blend structure, it is possible to grow GaAs on Ge with minimum defects. For a multijunction solar cell device, a thin layer of GaAs is first grown on the Ge substrate and followed by the growth of various other compositions. Existing III— V semiconductor multi-junction solar cells are processed from epitaxial gallium indium phosphide/gallium arsenide (GaInP2/GaAs) materials, grown on a GaAs nucleated Ge substrate. By providing active junctions in GaInPl, GaAs, and Ge, a triple-junction solar cell can be processed. These existing triple-junction solar cells have demonstrated a 29.3% efficiency under space solar spectrum that is Air Mass 0 (AMO), 0.1353 W/cml at 28° C. Under the concentrator terrestrial spectrum (AM1.5D, 44W/cm2, 25° C), an efficiency of 32.3% has also been demonstrated. The Air Mass value indicates the amount of air in space while the conversion efficiency describes a percentage of conversion from the sun's energy to electrical power. A limitation of such triple- junction solar cells includes the inability of increasing the AMO efficiency above 29.3% (to, for example, 35% or higher). To achieve such an increase, four junctions may be needed to enhance the utilization of the sun's energy spectrum.

Conventional methods to grow a triple-junction solar cell typically use GaInP2, GaAs and Ge cells. The direct bandgaps of GaInP 2 and GaAs are about 1.85 eV and about 1.424 eV respectively (Ge has an indirect bandgap of about 0.66 eV). Theoretical studies have shown that an additional third junction of about a 1.0 eV solar cell disposed on top of the Ge junction may be necessary for building a four junction monolithic solar cell. As such, GaInP2 may form the first junction, GaAs can form the second junction, a new 1 eV material may form the third junction and Ge can form the fourth junction. Limitations of such materials include a lack of a bandgap around 1.0 eVthat may be lattice matched to Ge and a lack of requisite material properties needed to process a solar cell. Some materials such as Gallium Indium Arsenic Nitride (GaInAsN) have been used in an attempt to achieve lattice-matching characteristics, however an ability to produce material with requisite characteristics and with a bandgap around 1.0 eVhas not been achieved. "

US 7122733 discloses the use of Boron-containing materials for use in forming IeV cell junctions. However, the use of boron is inherently problematic. Because boron is a small atom, its presence in a regular GaAs / Ge dimensioned crystal lattice causes stresses that can lead to crystal defects and poor carrier transport characteristics. For example, carrier lifetimes can be degraded as a result of these defects. This means that photo-generated carriers can recombine at these crystal defects and convert otherwise useful energy to waste heat, thereby degrading the conversion efficiency of the overall cell. There are also potential problems in the compatibility of source gasses used in MOCVD chambers to deposit boron and other compounds and the claimed innovation of using multiple buffer layers to promote correct growth of the boron containing layers is complex with potentially poor reproducibility.

Given the shortcomings of the 7122733 patent, a more simple approach is required which uses conventional materials and growth processes and which offers high degrees of manufacturing certainty and reproducibility.

From a different perspective, US patent 5223043, filed by Olson et al on 11 May 1992, assigned to US DoE and titled "Current Matched High Efficiency, Multi- Junction Monolithic Solar Cells", includes a general overview of issues relating to current matching in series connected cells. This patent is incorporated herein by reference.

In order to avoid the need for individual connections to each of the sub-cells in a multijunction cell, the subcells are implicitly connected in series as a result of the epitaxial growth process used to form them. Although this solves the connection problem, it introduces the need to match the currents produced by each subcell. Initial attempts at achieving this current match focused on modifying the material composition (and hence bandgaps) of the subcells so that they absorbed portions of the solar spectrum which resulted in equal photo-currents. The 5223043 patent points out that this is an overly restrictive means of achieving current matching given the relative difficulty of choosing lattice matched materials of the appropriate bandgap. Instead, the 5223043 patent claims the use of thinned subcell layers in dual layer (tandem) cells. When a subcell is made thinner than the minority carrier diffusion length of the semiconductor material used, the subcell becomes increasingly transparent to incoming light and its photo-generated current is reduced. If the upper subcell in a tandem cell structure generates more photocurrent than the lower subcell, current matching can therefore be achieved by thinning this upper subcell. Thinning the upper subcell not only results in a lowering of the current produced by the upper subcell, it also results in an increase in current produced by the lower cell because more light reaches this subcell. The 5223043 patent focuses exclusively on dual layer tandem cells comprising InGaP- GaAs, AlGaAs-GaAs and GaAs-Ge material layers. It does not teach skills required to produce multijunction cells comprising more than two subcell layers or techniques for increasing the efficiency of cells above the 27.3% quoted for AM 1.5 illumination.

Given the highly restricted scope of the 5223043 patent, there is a need for a more sophisticated multijunction cell design which offers higher conversion efficiency.

From a different perspective, in order to increase cell efficiency, currently cell manufacturers incorporate an additional photo-active junction in the substrate on which the other subcell layers are grown. Germanium is the preferred material used for multijunction manufacture because of its close match to the crystal lattice parameters of GaAs and other related III-V materials and its relatively low cost.

A recent US patent 7339109, filed by Stan et al on 19 June 2001, assigned to Emcore Corporation and titled "Apparatus And Method For Optimizing The Efficiency Of Germanium Junctions hi Multi- Junction Solar Cells", includes a useful overview of issues relating to formation of Ge subcells in prior art multijunction cells. This patent is incorporated herein by reference and provides the following summary:

"The energy conversion characteristic of a solar cell is dependent on the effective utilization of the available solar spectrum. Currently, a state-of-the-art solar cell is a multi-junction device that uses layers of indium gallium phosphide (InGaP), gallium arsenide (GaAs), and germanium (Ge). This triple-junction structure is based on an older dual-junction solar cell structure made of indium gallium phosphide (InGaP) and gallium arsenide (GaAs) covering the absorption spectrum from UV to 890 nm. The addition of a germanium (Ge) junction to the dual-junction structure extends the absorption edge to 1800 nm. Since the germanium (Ge) junction causes increased access to the solar- spectrum, the current generated in the germanium (Ge) junction is usually very high. The germanium (Ge) junction is not likely to limit the overall current of this serially connected multi-junction structure. Thus, the contribution of a germanium (Ge) junction improves the energy conversion efficiency by adding open-circuit voltage. Therefore, it becomes extremely important to optimize the open-circuit voltage of the germanium (Ge) junction without sacrificing the overall performance of the solar cell.

FIG. 1 [not included in this present specification] is a diagram that depicts the formation of a typical diffused germanium (Ge) junction on ap-type substrate. As FIG. 1 illustrates, the junction is formed by the diffusion of arsenic (As) and/or phosphorus (P) into the germanium (Ge) so that the conduction element ofp-type substrate is converted into n-type. Arsenic is an n-type impurity in germanium with a solubility, at metal organic chemical vapor deposition (MOCVD) growth temperatures, of 8x10 ¹⁹ cm3. In the prior art an electro- optically active germanium junction is formed as a consequence of arsenic diffusion into thep-type germanium substrate during the growth of arsenic- containing overlying epilayers.

A critical factor in maximizing the open circuit voltage characteristic is the control of the depth of the germanium (Ge) junction. As a consequence of the solid state diffusion process, the n-type germanium emitter is highly doped. As a result, most of the photo-generated carriers in this region will recombine before collecting at the n-p junction. This leads to an increased reverse saturation current (or referred to as "dark current") and in a concomitant reduction in the open circuit voltage (Voc) of the cell. Additionally, one would like to minimize the junction depth because the highly doped emitter region acts as an absorber of the incident long wavelength solar radiation. The increased absorption of long wavelength radiation causes lower short circuit current (Jsc) in the cell, which in turn, reduces the open circuit current of the stack. This results in less than optimum performance.

The depth of the diffused germanium junction is a function of the thermal load that results from the time-temperature profile of the epilayers grown on top of the p-type germanium substrate. Optimization of the germanium junction cannot be accomplished without affecting the subsequent dual junction epilayer device process. More specifically, to control the arsenic diffusion of the germanium substrate, the growth time and temperature of the overlying dual junction epilayer structure must be minimized. Thus, the integrity of the dual junction epilayer structure may be compromised to obtain an appropriate arsenic diffusion profile on the germanium substrate. "

The 7339109 patent goes on to describe a technique for minimising the diffusion depth of dopants from the middle subcell into the germanium substrate. The patent notes that Group V elements are the dominant species that diffuse into Ge and that arsenic diffuses approximately 4 times further into Ge than phosphorous does. The proposed technique therefore uses a layer of phosphorous containing material (InGaP) to form a diffusion barrier for arsenic-containing subcell layers. Instead, this layer provides a source of phosphorous atoms as n-type dopants for the Ge subcell. The advantage of this approach is that for a given heat load (temperature x time) phosphorous diffuses more slowly and forms a shallower junction. Quoted junction depths are reduced by 50%.

However, although this process provides a minor improvement in the control of junction depth, it also potentially introduces unfavourable band alignments in the region of the junction, in particular in the conduction band. This can create a barrier to carrier flow and increase cell resistance, thereby lowering efficiency. Secondly, diffusion processes are generally unreliable and do not produce uniform abrupt junctions. This means, for example, temperature needs to be controlled accurately across the entire wafer to ensure uniform diffusion and if it is not, cell yield can suffer. Finally, given the need for a high conductivity substrate, germanium junctions formed by diffusion are heavily compensated which leads to non-ideal subcell characteristics.

Given these shortcomings, there is a need for a multijunction cell structure which provides accurate control of germanium cell parameters at time of manufacture, which uses materials whose band alignment and carrier transport characteristics are optimised and which allows germanium doping densities to be chosen independently of other cell parameters.

From a different perspective, US patent 6340788, filed by King et al on 2 December 1999, assigned to Hughes Electronic Corporation and titled "Multi- Junction Photovoltaic Cells and Panels Using a Silicon or Silicon Germanium Active Substrate Cell For Space and Terrestrial Applications", describes the use of substrates other than germanium in multijunction structures. This patent is incorporated herein by reference. The 6340788 patent describes the use of silicon and silicon germanium as "active substrates" in multijunction cells. The attraction of silicon related materials is said to be because they are stronger, less expensive and less dense (which is important in space applications). The patent describes a series of elaborate 3, 4 and 5 junction cells wherein the substrate forms one of the active subcells. The patent also describes the use of so- called "transition layers" that are used to adjust the crystal lattice spacing from one value to another to facilitate the subsequent deposition of different materials with different lattice constants and bandgaps. The patent proposes the use of these transition layers at any place in the multijunction cell structure.

Although the 6340788 patent refers to known techniques for depositing transition layers, it is silent on the practicality of using these techniques to achieve low defect densities in subcell crystal lattices. This has been the central problem in prior art cells where materials are chosen from their bandgap properties alone. Without good crystal quality in the subcells, carrier lifetimes and overall cell efficiencies will be degraded in elaborate multijunction structures rather than being enhanced. The patent also proposes the use of multiple transition layers which potentially has a significant detrimental effect on crystal lattice quality.

Therefore there is a need for an improved strategy in the use of transition layers to achieve the best possible crystal quality. There is also a need for a new multijunction cell structure which optimises cell efficiency through the use of a more sophisticated choice of subcell materials.

The 6340788 patent also proposes the use of Si or SiGe substrates without consideration of the significant difference between the thermal expansion coefficient of silicon and the III-V semiconductors proposed for the multijunction subcells. For example the thermal expansion coefficient for Si is around 2.5 ppm per degree Celsius and GaAs is around 6ppm. This difference causes considerable degrees of stress in epitaxial films as they cool from growth temperatures of around 600 degrees Celsius to room temperature. In particular, since III-V materials shrink more than Si on cooling, significant crystal defects and even cracks can form. Therefore there is also a need for a new process for growing III-V multijunction cells on silicon substrates which overcomes the difficulties associated with differences in thermal expansion coefficients.

Accordingly, there is a demonstrable need for a new CPV cell module design that overcomes the shortcomings of the prior art. There is also a need for a method of manufacturing this new design at low cost.

The discussion throughout this specification comes about due to the realisation of the inventor and/or the identification of certain prior art problems by the inventor and, moreover, any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or before the priority date of the disclosure and claims herein.

OBJECT OF THE INVENTION It is an object of the present invention to overcome or ameliorate at least one of the disadvantages of the prior art, or to provide a useful alternative.

It is an object of the invention in its preferred form to provide an improved CPV device, or method of producing an improved CPV device.

SUMMARY OF THE INVENTION According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; and at least one epitaxial layer deposited on the substrate.

Preferably, the photovoltaic cell is a multijunction photovoltaic cell. More preferably, the impurity concentration of the inactive substrate is at least ten times greater than the average impurity concentration of the epitaxial layer or layers. Preferably, the inactive substrate is primarily comprised of germanium. Alternatively, the inactive substrate is primarily comprised of silicon.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; and a first epitaxial layer deposited on the substrate; wherein the first epitaxial layer comprises at least 95 percent germanium.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; and two or more epitaxial layers comprising Group IV semiconductors. According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; one or more subcells comprising Group IV semiconductors; and one or more subcells comprising Group III-V semiconductors; wherein the Group FV subcells and the Group III-V subcells are formed by means of epitaxial growth on the surface of the inactive substrate.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; a first subcell comprising germanium or silicon and germanium wherein silicon represents no more than 5 percent of the atomic composition; and a second subcell comprising silicon and germanium wherein silicon represents more than 5 percent and less than 30 percent of the atomic composition; and one or more subcells comprising Group III-V semiconductors;

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; one or more subcells comprising Group IV semiconductors; one or more subcells comprising Group III-V semiconductors; and at least one transition layer; wherein the at least one transition layer has a non-constant crystal lattice spacing and comprises Group IV semiconductors and the Group III-V semiconductor subcells have a fixed, unchanging crystal lattice spacing. 50

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According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; one or more subcells comprising Group IV semiconductors; one or more subcells comprising Group M-V semiconductors; and at least one diffusion barrier layer; wherein the at least one diffusion barrier layer is located between the Group IV semiconductor and the Group III-V semiconductor subcells.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive substrate; a first subcell comprising germanium or silicon and germanium wherein silicon represents no more than 5 percent of the atomic composition; and a second subcell comprising silicon and germanium wherein silicon represents more than 5 percent and less than 30 percent of the atomic composition; and one or more subcells comprising Group IH-V semiconductors.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive germanium substrate; a first subcell comprising germanium; a second subcell comprising silicon and germanium; a third subcell comprising gallium, arsenic and phosphorous; and a fourth subcell comprising indium, gallium and phosphorous; wherein the first subcell is deposited on the inactive substrate, the second subcell is deposited on the first subcell, the third subcell is deposited on the second subcell, and the fourth subcell is deposited on the third subcell.

Preferably, the second subcell comprises 17 percent silicon and 83 percent germanium. More preferably, the third subcell comprises 17 percent phosphorous and 83 percent Arsenic. Most preferably, fourth subcell comprises 40 percent indium and 60 percent gallium.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive germanium substrate; a first subcell comprising germanium; a second subcell comprising silicon and germanium; a third subcell comprising a gallium, arsenic and nitrogen; a fourth subcell comprising gallium, arsenic and phosphorous; and a fifth subcell comprising indium, gallium and phosphorous; wherein the first subcell is deposited on the inactive substrate, the second subcell is deposited on the first subcell, the third subcell is deposited on the second subcell; the fourth subcell is deposited on the third subcell and the fifth subcell is deposited on the fourth subcell.

Preferably, the second subcell comprises 17 percent silicon and 83 percent germanium. More preferably, fourth subcell comprises 17 percent phosphorous and 83 percent arsenic. Most preferably, fifth subcell comprises 40 percent indium and 60 percent gallium.

According an aspect of the invention there is provided a photovoltaic cell comprising: an inactive silicon substrate; a buffer layer deposited on the silicon substrate; one or more subcells comprising Group IV semiconductors deposited on the buffer layer; and one or more subcells comprising Group III-V semiconductors deposited on the

Group IV subcells; wherein the buffer layer comprises a region where the crystal lattice of the buffer layer has been modified after deposition to make it partly of fully amorphous and where the surface of the buffer layer is suitable for the epitaxial growth of the Group IV subcells.

Preferably, the modification is performed by ion implantation. The ion implantation is preferably performed at a temperature higher than room temperature. The ion implantation is preferably performed at approximately 120 degrees Celsius.

Preferably, the buffer layer is annealed at a temperature between 600 and 1100 degrees Celsius to reduce surface defects prior to deposition of the Group IV subcells. More preferably, buffer layer comprises SiGe. Most preferably, the buffer layer comprises SiGe and the proportion of Ge content of the buffer layer increases with distance away from the surface of the substrate.

Preferably, the surface of the inactive substrate is at an angle of between 3 and 9 degrees to the substrate crystal plane.

According an aspect of the invention there is provided a method of manufacturing a photovoltaic cell structure, the method comprising the steps of: epitaxially growing Group IV subcells on a substrate in a first growth chamber; transferring the substrate to a second growth chamber; and epitaxially growing Group III-V subcells on the substrate in a second growth chamber.

According an aspect of the invention there is provided a method of manufacturing a photovoltaic cell structure, the method comprising the steps of: epitaxially growing Group IV subcells on a substrate in a first growth chamber; depositing an oxidation barrier layer onto the surface of the Group IV subcells. transferring the substrate to a second growth chamber; heating the substrate to remove the oxidation barrier layer; and epitaxially growing Group III-V subcells on the substrate in a second growth chamber.

Preferably, the oxidation barrier layer is germanium.

According an aspect of the invention there is provided a photovoltaic module for converting concentrated light into electricity, the module comprising: a photovoltaic cell; and a printed circuit board comprising a first surface and a second surface; wherein the first surface and the second surface are in thermal communication; wherein the photovoltaic cell is in thermally communication with the first surface for coupling heat from the photovoltaic cell to the second surface. According an aspect of the invention there is provided a photovoltaic module for converting concentrated light into electricity, the module comprising: a photovoltaic cell; and a printed circuit board comprising a first surface and a second surface; wherein regions on the first and second surfaces are joined by a plurality of metallic structures extending from the first surface to the second surface; and wherein the photovoltaic cell is attached directly or indirectly to the first surface of the printed circuit board and the metallic structures couple heat from the photovoltaic cell to surfaces operatively coupled to the second surface of the printed circuit board.

According an aspect of the invention there is provided a photovoltaic module for converting concentrated light into electricity comprising: a photovoltaic cell; an electrically insulating substrate having thermal conductivity of greater than 10 watts per metre-Kelvin; and a printed circuit board comprising a first surface and a second surface; wherein regions on the first and second surfaces are joined by a plurality of metallic structures extending from the first surface to the second surface; and wherein the electrically insulating substrate is attached to the first surface of the printed circuit board and the photovoltaic cell is mounted on the electrically insulating substrate and where heat is coupled from the photovoltaic cell, through the electrically insulating substrate and through the metallic structures to surfaces operatively coupled to the second surface of the printed circuit board. According an aspect of the invention there is provided a photovoltaic module for converting concentrated light into electricity comprising: a photovoltaic cell; a printed circuit board comprising a first surface and a second surface; and an electrically insulating cover assembly comprising a cavity, an external surface and a plurality of apertures which extend from the external surface to the cavity; wherein the photovoltaic cell and the electrically insulating cover assembly are attached directly or indirectly to the first surface of the printed circuit board and where the photovoltaic cell is located within the cavity of the cover assembly.

According an aspect of the invention there is provided a photovoltaic module for converting concentrated light into electricity comprising an optical aperture and a detachable protective layer covering the optical aperture.

According an aspect of the invention there is provided a method of manufacturing a plurality of photovoltaic modules comprising the steps of:

(a) providing a printed circuit panel comprising a plurality of circuit boards; (b) depositing photovoltaic cells sequentially onto each circuit board;

(c) connecting photovoltaic cell terminals to metallic features on each circuit board using bond wires;

(d) attaching electrically insulating cover assemblies comprising cavities and optical apertures to each circuit board such that the components and the photovoltaic cells are located within the cavities and the optical aperture is aligned with the active surface of the photovoltaic cells;

(e) depositing optically transparent adhesive into the cavities;

(f) placing coverglass structures into the optical apertures and in contact with the optically transparent adhesive; and (g) curing the optically transparent adhesive to seal the module and permanently fix the coverglass structures in place.

According an aspect of the invention there is provided a method of manufacturing a plurality of photovoltaic modules comprising the steps of: loading a printed circuit panel comprising a plurality of circuit boards into an automated component placement machine; depositing electronic devices sequentially onto each circuit board; depositing photovoltaic cells sequentially onto each circuit board; connecting photovoltaic cell terminals to metallic features on each circuit board using bond wires; attaching electrically insulating cover assemblies comprising cavities and optical apertures to each circuit board such that the components and the photovoltaic cells are located within the cavities and the optical aperture is aligned with the active surface of the photovoltaic cells; depositing optically transparent adhesive into the cavities; placing coverglass structures into the optical apertures and in contact with the optically transparent adhesive; curing the optically transparent adhesive to seal the module and permanently fix the coverglass structures in place; separating each of the circuit boards contained on the printed circuit panel, including attached module elements, to form individual photovoltaic modules; and attaching electrical interconnection means to each module.

According an aspect of the invention there is provided a method of cleaning an optical aperture of a photovoltaic module used in a concentrating solar energy converter, the method comprising the steps of : applying a film comprising an adhesive layer to the surface of the optical aperture, the adhesive being removable without leaving any residue on the surface; and removing the film from the surface.

Preferably, the photovoltaic cell is a multi-junction cell. More preferably, the photovoltaic cell is a multi-junction cell as herein described. Most preferably, the photovoltaic cell is a multi-junction cell as herein described with reference to the drawings.

Preferably, the printed circuit board is a printed circuit board. More preferably, bond wires are used to couple the photovoltaic cell terminals to metallic tracks on the first surface of the circuit board. Most preferably, bond wires comprise aluminium or gold.

Preferably, attachment comprises use of a conductive adhesive or a solder. More preferably, attachment comprises use of electrically conductive or thermally conductive adhesive or solder.

Preferably, each of the plurality of metallic structures is a via hole. More preferably, each of the plurality of metallic structures is a plated via hole. Most preferably, each of the plurality of metallic structures is a via hole that is completely filled with metal. Copper is preferably used in each of the plurality of metallic structures.

Preferably, the electrically insulating substrate is a ceramic. More preferably, the electrically insulating substrate is aluminium nitride.

Preferably, at least one aperture is in optical alignment with the photovoltaic cell. More preferably, at least two aperture are each shaped to accept a module electrical interconnection. Most preferably, the electrical interconnection are plastic insulated metallic wires.

Metallic conductors are preferably, embedded in the insulating cover assembly and arranged to make contact with the interconnection when inserted in the respective aperture. These metallic conductors preferably comprise retaining features such as teeth, barbs, clamps or projections which prevent withdrawal of the interconnection after insertion. The electrical interconnection is connected to the metallic conductors using electrically conductive adhesive or solder. The interconnection is preferably bonded to the module cover assembly aperture using electrically insulating adhesive. The electrically insulating adhesive is preferably an epoxy preform.

Preferably, electronic components are coupled to the first surface of the printed circuit board such that they fit within the cavity of the cover assembly. More preferably, the cavity in the module cover assembly is filled with optically transparent adhesive. This optically transparent adhesive preferably adheres to and retains a coverglass element positioned into the aperture in optical alignment with the photovoltaic cell. The adhesive is preferably deposited under vacuum. The adhesive preferably provides a high voltage isolation barrier. Preferably, the adhesive is a silicone adhesive. Alternatively, is preferably an adhesive is an epoxy adhesive. Preferably, the adhesive has a Shore Hardness of approximately 30. The coverglass structures preferably comprise a glass substrate and an anti-reflective coating.

Preferably, the insulating cover assembly comprises an organic polymer. More preferably, the insulating cover assembly comprises a thermosetting organic polymer. Most preferably, the insulating cover assembly comprises a thermoplastic organic polymer. The insulating cover assembly preferably comprises a ceramic. The insulating cover assembly preferably insulating cover assembly comprises glass. Alternatively, the insulating cover assembly can preferably comprise a thermosetting polymer. More preferably, the insulating cover assembly comprises a thermoplastic polymer.

Preferably, the insulating cover assembly is produced, in part, by a moulding or casting process. More preferably, the moulding process is an insert moulding process.

Preferably, the module cover assembly comprises apertures or inserts used to attach the module to a panel or to attach other structures or components to the module. More preferably, the module cover assembly is shaped to match the contour of other structures or components mounted onto the module.

The module preferably comprises an optical aperture which is protected by a detachable adhesive layer. Preferably, the detachable protective layer comprises an adhesive.

Preferably, an automated assembly machine is a surface mount technology (SMT) assembly machine.

Preferably, electronic devices comprise at least one diode and/or microcontroller and/or resistor and/or capacitor and/or transistor.

Preferably, the insulating cover assembly comprises embedded electrical conductors. The embedded electrical conductors preferably mechanical retain a module electrical interconnection, when inserted.

Preferably, attaching an electrically insulating cover assembly comprises selective deposition of an electrically conductive adhesive or solder paste. Preferably, attaching an electrically insulating cover assembly comprises deposition adhesive preforms which are rigid in their uncured state. Preferably adhesive preforms comprise epoxy.

Preferably, a vacuum is applied to the circuit board panel and associated module components during or after deposition of an optically transparent adhesive.

Curing preferably comprises heating the printed circuit panel above ambient temperature for a prescribed time. Separating of the circuit boards preferably comprises mechanical punching or sawing or cutting by mechanical means or by laser.

Preferably, attaching an electrical interconnection comprises: applying a prescribed amount of conductive adhesive or solder paste into apertures in the cover assembly which contain embedded metallic conductors which are in electrical contact with the photovoltaic cell terminals; inserting electrical interconnection means into the aperture such that an exposed electrically conductive portion of the interconnection means comes into contact with both the embedded metallic conductors and the conductive adhesive or solder paste; inserting an electrically insulating adhesive preform around the electrical interconnection means at the point where it enters the cover assembly aperture; and heating the module assembly and interconnection means to cure adhesives and / or to refiow solder paste.

Preferably, the method of manufacturing a plurality of photovoltaic modules comprises performing the steps in the order listed. Preferably, the method of manufacturing a photovoltaic module further comprises the step of applying a removable protective layer over the optical aperture of the photovoltaic module. More preferably, the removable protective layer comprises an adhesive that can be peeled off the optical aperture without leaving any residue.

Preferably, applying the film comprises spraying a liquid adhesive compound onto the surface of the optical aperture and allowing or forcing it to dry to form a pliable or elastic removable layer.

According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems comprising industry standard components which are suited to high volume, automated, low cost manufacture.

According to an aspect of the invention there is provided a method of manufacturing a cell module structure for concentrator photovoltaic subsystems using industry standard manufacturing processes suited to high volume, automated, low cost manufacture. According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems which can be manufactured with highly reproducible characteristics.

According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems which is environmentally sealed and immune from environmental effects such as ingress of moisture or pollutants.

According to an aspect of the invention there is provided provides a cell module structure for concentrator photovoltaic subsystems comprising a removable protective barrier that seals the optical surface of the module after manufacture and which is removed prior to operation after the module is installed in a panel.

According to an aspect of the invention there is provided a method of cleaning cell module structures in concentrator photovoltaic subsystems comprising the steps of applying a temporary polymer adhesive in a liquid state to the surface of the module, allowing or forcing the polymer to dry to from a pliable sheet and peeling the sheet away from the surface of the module.

According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems which offers improved high voltage isolation between cell contacts and external surfaces of the module.

According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems which offers improved mechanical robustness and which has increased tolerance to mechanical stresses applied during shipping, handling and operation.

According to an aspect of the invention there is provided a cell module structure for concentrator photovoltaic subsystems which offers structural support for adjoining subsystem elements.

According to an aspect of the invention there is provided a photovoltaic cell for an optically concentrating energy conversion system, the photovoltaic cell comprising: one or more metallic contact layers for enabling electrical contact to the cell.

According to an aspect of the invention there is provided a photovoltaic cell structure for use in optically concentrating energy conversion systems comprising metallic contact layers used to make electrical contact to the cell wherein the predominant component of the metallic contact layers is copper.

According to an aspect of the invention there is provided a photovoltaic cell structure for use in optically concentrating energy conversion systems, the photovoltaic cell comprising a contact metallisation pattern wherein metallic contacts are deposited on the surface of the cell in patterns which extend from a plurality of discrete contact pads, the majority of the contact pads each being less than 5% of the total cell area.

According to an aspect of the invention there is provided a method of manufacturing a photovoltaic cell structure for use in optically concentrating energy conversion systems, the method comprising the steps of:

(a) providing a multijunction wafer having a germanium substrate, multijunction epitaxial structure, a low bandgap semiconductor surface layer, and a surface oxide layer on the low bandgap layer;

(b) removing the surface oxide layer; (c) depositing a surface adhesion layer;

(d) depositing a first photoresist layer;

(e) deposition of an alloying contact layer;

(f) removal of the first photoresist layer;

(g) annealing a back contact layer; (h) depositing a second photoresist layer;

(i) exposing and developing the second photoresist layer;

(j) depositing a contact metal;

(k) removal of the second photoresist layer; (1) etching a adhesion layer and a diffusion barrier layer;

(m) etching to selectively remove ohmic contact layer;

(n) depositing third photoresist layer;

(o) exposing and developing the third photoresist layer;

(p) etching to remove epitaxial layers; (q) removal of third photoresist;

(r) depositing an anti reflective coating layer;

(s) deposition a fourth photoresist layer;

(t) exposing and developing the forth photoresist layer; and

(u) etching the anti-reflective coating.

Preferably, the dominant component of the metallic contact layers is copper. The copper is preferably deposited by electroplating.

Preferably, the photovoltaic cell is a multijunction cell. More preferably, the photovoltaic cell is a multijunction cell as herein described.

Preferably, the metallic contact layers comprise an adhesion layer for promoting adhesion of the metallic contact layers to the cell. The adhesion layer is preferably titanium, nickel or chromium.

Preferably, the metallic contact layer comprises a diffusion barrier layer. The diffusion barrier layer is preferably titanium nitride.

Preferably the metallic contact layer comprises an alloying contact layer which diffuses into the cell surface on heating and forms an ohmic contact. The alloying contact layer preferably comprises gold.

Preferably, the contact layer is elongate. More preferably, contact layer is elongate and extends away from an active surface of the multijunction cell to thereby obscure obscures a relatively small percentage of the active surface. Preferably, the one or more metallic contact layers define a contact metallisation pattern; wherein metallic contacts are deposited on the surface of the cell in patterns which extend from a plurality of discrete contact pads. More preferably, the contact pads each occupy less than 5% of the total cell area. Most preferably, the discrete contact pads are located around the periphery of the cell. Bond wires are preferably used to make contact with the discrete contact pads.

Preferably, the contact metallisation pattern extends from the contact pads towards the centre of the cell.

The contact metallisation pattern preferably has either a fractal geometry, a regular or symmetric geometry, or an irregular or asymmetric geometry.

Preferably, the method of manufacturing a photovoltaic cell structure for use in optically concentrating energy conversion systems further comprises the step of: dicing of the wafer to form individual cells. More preferably, the method further comprises the step of: removing the fourth photoresist from the individual cells. Most preferably, the method provides one or more metallic contact layers to define a contact metallisation pattern; wherein metallic contacts are deposited on the surface of the cell in patterns which extend from a plurality of discrete contact pads.

According to an aspect of the invention there is provided a multijunction photovoltaic cell comprising low cost metal contact structures which are safe and easy to deposit.

According to an aspect of the invention there is provided a multijunction photovoltaic cell comprising non-alloyed ohmic contacts to the photoactive side of the cell which serve as a diffusion barrier.

According to an aspect of the invention there is provided a multijunction photovoltaic cell comprising contact metallisation which is more closely matched to the thermal expansion characteristics of the cell semiconductor material than conventional materials.

According to an aspect of the invention there is provided a method of manufacturing a multijunction photovoltaic cell which provides the above advantages. According to an aspect of the invention there is provided a photoactive side contact pattern which obscures only a small portion of the active area of the cell and which is suited to wire bonding.

According to an aspect of the invention there is provided a multijunction photovoltaic cell structure with improved conversion efficiency comprising at least three subcells on an inactive substrate.

According to an aspect of the invention there is provided a method of manufacturing the multijunction photovoltaic cell structures.

According to an aspect of the invention there is provided a multijunction photovoltaic cell structure comprising Group IV and Group III-V subcells formed by epitaxial growth on a low cost inactive substrate.

According to an aspect of the invention there is provided a 4 and 5 junction cell designs offering improved conversion efficiencies.

According to an aspect of the invention there is provided a multijunction photovoltaic cell structure comprising a silicon substrate and an amorphous stress relieving layer.

According to an aspect of the invention there is provided a method of manufacturing multijunction cells incorporating lattice transition layers and buffer layers which improve manufacturability.

According to an aspect of the invention there is provided a method of manufacturing multijunction cells comprising both Group IV and Group III-V subcells comprising use of separate growth chambers.

According to an aspect of the invention there is provided a method of manufacturing multijunction cells comprising use of an oxidation barrier layer to protect substrate surfaces as they are transported between growth chambers. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

FIG. 1 is a perspective view of a CPV panel assembly using Fresnel lenses.

FIG. 2 is an enlarged perspective view of the assembly of FIG. 1.

FIG. 3 A is a perspective view of a CPV subsystem using cassegrain reflectors;

FIG. 3B is a cross section of the subsystem of FIG. 3 A showing internal details;

FIG. 4 is a perspective view of a CPV cell module using industry standard integrated circuit packages;

FIG. 5 is a perspective view of a CPV cell module;

FIG. 6 is a perspective view of a CPV module;

FIG. 7 is an inline for assembly view of a cassegrain CPV module assembly.

FIG. 8A is an isometric view of a photovoltaic module according to an embodiment of the present invention.

FIG. 8B is a cross section of a photovoltaic module of FIG. 8 A, showing internal detail.

FIG. 8C is an enlarged view of a photovoltaic cell assembly of FIG. 8 A.

FIG. 8D is a view of a cover assembly of FIG. 8 A, showing hidden detail.

FIG. 8E is a cross section view of a cover assembly of FIG. 8D.

FIG. 8F is a view of an alternate photovoltaic module according to an embodiment of the present invention.

FIG. 8G is a view of a circuit board structure of FIG. *A. FIG. 9A is a view of a circuit board panel according to an embodiment of the present invention.

FIG. 9B is a view of an assembly step for a circuit board panel of FIG. 9 A.

FIG. 9C is a view of a partially assembled circuit board panel of FIG. 9A.

FIG. 9D is another view of a further partially assembled circuit board panel of FIG. 9A.

FIG. 9E is a view of a completely assembled circuit board panel of FIG. 9 A.

FIG. 9F is a view of a completely assembled circuit board panel of FIG. 9 A, including protective layers.

FIG. 9G is a view of assembled modules which have been separated from the circuit board panel of FIG. 9 A.

FIGs 1OA to 1OD show a detailed assembly sequence according to an embodiment of the present invention.

FIGs 1 IA to 11C show an alternate version of certain assembly steps according to an embodiment of the present invention.

FIG. 12 shows a flowchart for a manufacturing method according to an embodiment of the present invention.

FIGs 13 A to 13D show a method of cleaning photovoltaic modules according to an embodiment of the present invention.

FIG. 14 is a diagrammatic view of a multijunction cell.

FIG. 15 is a plan view of a multijunction cell.

FIG. 16 is a plan view of a multijunction cell.

FIG. 17 is a cross section view of a multijunction cell according to an embodiment of the present invention. FIGs 18A through 18F show a manufacturing sequence the multijunction cell of to FIG. 17.

FIG. 19 shows a contact metallisation pattern according to an embodiment of the present invention.

FIG. 20 shows a contact metallisation pattern according to an embodiment of the present invention, including bond wires.

FIG. 21 A shows a simplified view of a multijunction cell according to an embodiment of the present invention.

FIG. 21B shows a simplified view of the multijunction cell of FIG 2 IA, including transition layer and diffusion barrier layer.

FIG. 21 C shows a simplified view of the multijunction cell of FIG 21 A, showing individual Group IV subcells.

FIG. 2 ID shows a simplified view of the multijunction cell of FIG 2 IA, showing individual Group IV subcells and transition and diffusion barrier layers.

FIG. 22 A shows a detailed view of a four junction cell according to an embodiment of the present invention.

FIG. 22B shows a detailed view of a five junction cell according to an embodiment of the present invention.

FIG. 23 A shows a simplified view of a multijunction cell according to an embodiment of the present invention, showing an oxidation barrier layer deposited on top of Group IV subcells after subcell growth and before transfer to a second growth chamber.

FIG. 23 B shows a simplified view of a multijunction cell according to an embodiment of the present invention showing removal of the oxidation barrier layer prior to growth of Group III- V subcells in a second growth chamber. FIG. 23 C shows a simplified view of a multifunction cell according to an embodiment of the present invention showing the cell after growth of the Group III-V subcells in the second chamber.

FIG. 23D shows a simplified flow chart of the process used to make the multijunction cell according to an embodiment of the present invention.

FIGs 24A to 24D show the steps of making a multijunction cell on a silicon substrate according to an embodiment of the present invention.

PREFERRED EMBODIMENT OF THE INVENTION

In order to provide clarification for the accompanying description and claims, the following definitions are provided:

> The term "CPV" is an abbreviation of Concentrator Photo-Voltaic and refers to optical to electric power conversion systems using optical concentrators to collect and focus light onto photovoltaic cells;

> the term "CPV subsystem" is used to mean the combination of a cell module plus optical concentrating elements which focus light onto the cell module plus mechanical structures used to support and / or house the optical elements and the cell module; and

> the term "panel" means an array of subsystems that are assembled and interconnected to form a single rigid structure.

y the terms "module" or "cell module" are used to mean the combination of the cell plus the structure immediately surrounding the cell, including means of making electrical contacts to the cell, means of dissipating waste heat from the cell and means of providing structural support or mounting for the cell and adjoining subsystem elements;

> the term "cell" is used to mean the semiconductor device which converts light into electrical energy; > the term "sub-cell" is used to mean a particular portion of the overall cell comprising a semiconductor p-n junction that is responsive to a specific range of wavelengths of light.

> the term "multijunction cell" is used to mean a photovoltaic cell comprising multiple semiconductor layers having different doping and material properties and which are layered to form multiple photovoltaic junctions connected in series;

> The terms "dopant" or "doped" refer to elements which are deliberately introduced into a semiconductor crystal lattice to obtain desirable electrical or optical properties.

> The term "impurity" is used to refer to elements that are inadvertently incorporated into a semiconductor material as a result of imperfect refinement or manufacturing processes.

Photovoltaic module Embodiments will now be described in relation to the drawings. Where possible, unique numbers have been used to identify the same element in each drawing or sub-drawing. The terms "upper" and "lower" are intended to aid description of the drawings as shown and are not meant to restrict the scope of the invention.

Referring to FIG. 8A, an example embodiment is shown that provides an integrated CPV cell module 800a comprising a low cost industry standard circuit substrate 801a with an insulating cover assembly 802a fixed to its surface. This cover assembly is made from an electrically insulating material which encloses the photovoltaic cell (not shown in FIG. 8A) and provides an environmental seal and a high voltage isolation barrier. The cover assembly also provides mechanical features which can be used both for mounting the cell module onto a panel housing and for mounting other structures onto the cell module. These features preferably include apertures 842a into which fastening devices such as screws or bolts 812a / 813a are inserted. The apertures preferably extend partially through the cover assembly and may be shaped to accept the fasteners. For example the apertures themselves may be treaded to accept a screw or may have an insert fitted in them such as commercial Nutsert devices which, provide threaded features. Alternatively, the apertures 842a extend from one side of the cover assembly to the other such that other fasteners such as nuts and bolts can be used.

The cover assembly may also include other surface features such as recesses or protruding lugs that mate with corresponding features on the system into which the cell module is mounted, thereby serving to locate of fix the cell module in the CPV subsystem.

As an example, the cover assembly provides a means of mounting adjoining cell module features such as a metallic optical guiding structure 811a.

As a further example, the overall dimensions of the cell module may be 25mm x 25mm x 10mm (excluding attached optical guiding structures).

The cell module also comprises an optically transparent aperture 804a on one face that allows light into the cell module.

Cover assembly 802a also includes apertures 815a for accepting cell module interconnect features such as plastic insulated cylindrical wires 806a. These apertures 815a are preferably designed to fit closely around the ends of the wires such that the wires can be secured using adhesives (not shown) such as epoxies. In this way the cover assembly provides mechanical support for the wire and prevents stresses applied to the wires from being coupled to the internal components of the cell module. Although wires are preferred for reasons of low cost, the use of other interconnection means such as flexible laminated circuit structures can be used in an embodiment.

Secondly, the adhesive used to secure the wires provides both an environmental seal and a high voltage isolation barrier. The epoxy may be applied in liquid form and cured or may be applied using so-called performs which are solid structures shaped to suit the assembly and which flow and seal the unit when cured at elevated temperatures. Although epoxies are preferred, other types of adhesives can be used in an embodiment.

FIG. 8B provides a cross section view of the module shown in FIG. 8 A including location of panel housing 814b which is not shown in FIG. 8 A. The cell module is assembled on an industry standard circuit board 801b which is preferably made from low cost material such as FR4. The circuit board has metal features on both sides and includes thermal via structures 820b. Details of these and other features of this circuit board are provided in the following sections.

Solar cell assembly 803b is mounted on top of circuit board 801b. The electrical connections of the cell assembly are connected to tracks on the upper surface of the circuit board preferably using industry standard bond wires. The cell assembly and circuit board are thus arranged according to common industry practices known as "chip- on-board" or "direct chip attach". Additional electrical components 808b such as bypass diodes are also preferably mounted on the upper surface of the circuit board near the cell assembly 803b. These components are preferably industry standard surface mount components that do not require mounting holes through circuit board 801b.

Cover assembly 802b comprises a cavity 807b which accommodates the cell assembly and other components mounted on the upper surface of the circuit board. The cell module comprises a coverglass component 804b made of optically transparent material such as borosilicate glass which preferably has an anti-reflection coating (ARC) 805b on the surface exposed to incoming light. This anti-reflective coating for example may be comprised of a combination of titanium oxide, aluminium oxide or magnesium fluoride.

As noted in FIG. 8 A, cover assembly 802b includes apertures 815b which accommodate ends of interconnect wires 806b. The cover assembly also comprises embedded electrical connections 810b which provide connection between the ends of interconnect wires where wire insulation has been removed 826b and the metallic tracks on the upper surface of the circuit board. These embedded electrical connections are preferably incorporated into cover assembly at the time it is formed. Alternatively, the electrical connections may be inserted into recesses in the cover assembly after it is formed. For example, the electrical connections are metallic structures that may be formed by pressing, stamping and/or bending and which are press-fitted into recesses in the insulating cover assembly after it is formed.

The embedded electrical connection structures preferably incorporate features such as barbs, teeth or clamps which allow interconnection means such as wires to be inserted into the connector and which then mechanically press against or bite into the wire, preventing its removal. In this way an embodiment can enable wires to be inserted into the cover assembly and retained until they are permanently secured by conductive adhesive or solder.

Cover assembly 802b is preferably made by a moulding or casting process such as "insert moulding" which is capable of incorporating metallic conductors 810b in the assembly at the time it is produced. As noted above, the cover assembly is electrically insulating and is preferably made from a polymer, glass or ceramic. Most preferably it is made from a thermosetting polymer which provides low cost and mechanical stability at elevated temperatures.

FIG. 8C provides a magnified view of the cell assembly 803. Circuit board 801c is preferably an industry standard circuit board or printed circuit board (PCB) comprised of an insulating core 823c, patterned metallic surfaces 822c and 824c and via structures 820c. The term "industry standard circuit board" refers to a circuit board where the core material 823 c is a low cost circuit material such as FR-4 (Woven glass and epoxy) or other similar materials such as FR-2 (Phenolic cotton paper), FR-3 (Cotton paper and epoxy), FR-5 (Woven glass and epoxy), FR-6 (Matte glass and polyester), G-10 (Woven glass and epoxy), CEM-I (Cotton paper and epoxy), CEM-2 (Cotton paper and epoxy), CEM-3 (Woven glass and epoxy), CEM-4 (Woven glass and epoxy), CEM-5 (Woven glass and polyester), various polymers such as polyimide or Teflon and proprietary materials such as Getek and Arlon. The key characteristics of the core material are operational temperature stability to at least 150 degrees Celsius and sufficient dielectric strength to provide high voltage isolation between upper and lower surface of the circuit board. Metallisation deposited on such industry standard circuit boards is preferably copper.

Prior art CPV cell modules use exotic substrates made from materials such as aluminium nitride. Although these materials provide good thermal conductivity and electrical isolation, they are expensive and cannot be economically produced in large sheets. Therefore, prior art CPV cell modules are individually assembled from small parts which makes high volume manufacture difficult. The inventor has realised that a different approach can overcome this difficulty. By using industry standard circuit boards as a substrate, many cell modules can be assembled simultaneously on large panels using standard automated assembly machines, thereby lowering costs. The inventor has further realised that the problem of poor thermal conductivity of the circuit board can be overcome using metallised via holes and that thermal conductivity can be increased to the point where only a small temperature gradient occurs across the circuit board structure. For example, in CPV systems with optical concentration of 500 times, and with an incident radiation density of 1000 watts per square metre, the temperature gradient across the circuit board structure of an embodiment can be kept below 4 degrees Celsius.

To achieve this, via structures 820c are made in circuit board 801c using industry standard manufacturing processes. Preferably these via holes are made by electroplating and are completely filled with metal to increase thermal conductivity. Additional details of the thermal via structures are provided in a following section.

Although the use of standard circuit board material and thermal vias solves manufacturing and thermal management difficulties, it does not address the need for electrical insulation between the cell and the panel housing which is in contact with the lower surface of the cell module. The inventor has realised that a small piece of high thermal conductivity, insulating material, such as aluminium nitride can be positioned on top of the thermal vias to overcome this problem. The amount of exotic substrate material can therefore be reduced to an area only slightly larger than the photovoltaic cell itself, thereby reducing costs.

As shown in FIG. 8C, insulating substrate 830c is fixed to circuit board 801c using thermally conductive layer 831c. This layer is comprised of adhesive, solder or a eutectic metal alloy. Preferably, this layer is comprised of epoxy adhesive which contains particles having high thermal conductivity. For example, an epoxy incorporating silver flakes or diamond particles is used. It does not matter whether this layer is electrically conductive or not because electrical insulation is provided by the above insulating substrate 830c.

Insulating substrate 83Oc preferably has a metal layer 832c deposited on one surface. This layer is formed by evaporation, sputtering and/or electroplating and is preferably less than 50 microns thick. The layer provides a lateral connection for the lower terminal of the solar cell to a region where bond wires 809c or other electrical contacts can be made. Solar cell 834c is fixed to the metallic surface 832c of insulating substrate 83Oc using another layer of adhesive, solder or a eutectic metal alloy. Preferably, this layer is comprised of epoxy adhesive which also contains particles which provide high thermal conductivity and electrical conductivity. A silver filled epoxy is preferable.

Metallisation on the surface of circuit board 801c is patterned to form a gap 825c between surface features connected to the solar cell terminals 821c and metal connected to the thermal via structures 824c. This gap provides part of the high voltage isolation barrier of the cell module.

Referring again to FIG. 8B, cavity 807b is filled with an optically transparent material that fixes coverglass 804b in place. This material also bonds to the surface of the circuit board in gap regions 825c mentioned above and enhances the ability of the module to tolerate high voltages between cell contacts and the base of the cell module. This material is chosen for its optical clarity, its ability to flow and fill voids in the cover assembly cavity and its stability in the presence of elevated temperatures, light (particularly ultraviolet light) and high voltages. This material is preferably silicone or epoxy. The material may be applied under vacuum to ensure it fills all voids inside the cell module.

FIG. 8D provides a view of cover assembly 802a-d as it is manufactured prior to assembly in the cell module. As noted above the cover assembly comprises apertures for accepting interconnection wires 815d, locating fixing means such as screws 842d, central cavity 84Od, optical aperture 84 Id and metallic inserts 810d used to connect interconnection wires to circuit board features.

FIG. 8E provides a cross section view of the cover assembly shown in FIG. 8d including reference numbers according to the previously mentioned elements. The cover assembly also comprises a ledge feature 843 e which is used to support the coverglass at a prescribed distance above the cell while adhesive used to fill cavity 84Oe cures.

The cell modules in FIGs 8A through 8E are shown with rectangular features. However modules with different shapes and sizes can be used in an embodiment. For example. FIG. 8e shows a cell module comprising features of an embodiment and including a cover assembly 802f that has a curved, concave upper surface. This type of module suits cassegrain optical concentrators where the primary reflector 85 If is attached directly to the cell module. The cell module in this design is also adapted to take a different coverglass assembly 852f which provides a light guiding function.

FIG. 8G shows a basic design of the cell module circuit board layout including thermal vias 82Og, electrical connection regions 82 Ig and metallised heat spreading regions 822g and 824g. The thermal vias are formed by first drilling holes in the circuit board and then plating metal, such as copper into the hole. Preferably the thermal vias of an embodiment are completely filled by metal during the plating process, thereby providing maximum thermal conductivity. The holes are made as small as possible within the capabilities of industry standard processes and are approximately 0.3 millimetres in diameter, or less. The holes are placed as close together as possible which typically results in a hole to hole spacing of approximately 0.3 millimetres. Although, holes are preferred, other thermal via shapes can be used in an embodiment. For example, elongated holes or slots may be formed and filled with electroplated metal. In this way the percentage of copper in the circuit board under the cell can be increased. It is important that the holes are made small for two reasons: 1) the holes need to be filled by electroplating and 2) if the holes are small compared to the thickness of the insulating substrate 830c, this substrate will act as a heat spreader and there will be minimal lateral thermal gradient across the surface of the PV cell.

By using round thermal via holes which are spaced one hole diameter apart, the inventor has calculated that the bulk thermal conductivity of the circuit board increases to approximately 91 watts per metre Kelvin (W/mK) compared to only 0.3 W/mK for circuit boards without thermal vias. If the circuit board thickness is 0.8 mm and incident optical energy is 50 watts per square centimetre, the temperature gradient occurring across the circuit board is approximately 4.4 degrees Celsius. This temperature rise does not significantly degrade cell performance and is acceptable in system designs. The use of low cost circuit board substrates and thermal vias of an embodiment allows cell modules to be manufactured reproducibly in high volume with improved performance at reduce costs.. From another perspective, an embodiment provides a simple, low cost method of reproducibly manufacturing concentrator photovoltaic cell modules with improved mechanical and environmental robustness and improved high voltage isolation.

An embodiment, preferably uses industry standard manufacturing processes and components to lower costs. FIG. 9A shows a circuit board panel 900a which forms the base of a plurality of cell modules. As described earlier in this specification, this panel is made from industry standard circuit board material such as FR4, has patterned metal on both sides and has thermal via structures at the location where cells are to be mounted (not shown). Each cell module, is separated from adjacent cell modules by slots 902a and 903 a such that after assembly the circuit board panel can be easily cut to form individual modules. The panel is made as large as possible to allow assembly of as many modules as possible in one assembly sequence. For example, industry standard sizes for circuit board panels are 18 x 24 inches (457 mm x 610 mm). Preferably, the manufacturing process starts with a circuit board panel of this size. Therefore, if each module base measures 25 x 25 mm (including separation slots 902a and 903a) approximately 432 modules would be assembled on each panel. However, automated component placement machines may require a smaller panel size than this, in which case a smaller panel is preferred.

Referring to FIGs 9B and 9C, components 905b including the PV cell assembly and other devices such as bypass diodes are placed on each of the cell module bases to form a uniform array of modules 910c. Components are mounted using industry standard techniques involving either conductive adhesives or soldering processes.

Referring now to FIGs 9D and 9E, after the cell assembly and other components have been mounted on each module, cover assemblies are 906d are sequentially mounted onto the circuit board panel to produce a uniform array of modules 92Oe.

Prior to separating the individual modules, a protective film 907f may be optionally applied to the optical aperture of each module to prevent contamination or damage to the coverglass ARC coating, as shown in FIG. 9f. Alternatively, this protective film may be applied at a later stage in the process sequence, or not at all. The next step in the manufacturing sequence is to separate each circuit substrate to from a plurality of modules 94Og as shown in FIG. 9g. This is done by industry standard techniques such as punching, milling or cutting by mechanical means or by laser.

Following separation, interconnect means such as wires are attached to each module and other components such as optical guiding structures are fixed to the module cover assemblies.

A detailed description of an example embodiment of this process is now provided with reference to FIGs 1OA to 10D. It should be noted that although each manufacturing step is numbered for descriptive clarity, the process shown is exemplary. Specifically, certain process steps may be performed in a different order or omitted.

The following Steps 1 to 10 are preferably performed on a circuit panel that contains multiple cell modules. The assembly process preferably uses industry standard surface mount technology (SMT) pick and place machines.

Step 1 comprises loading a bare printed circuit panel 1001 into an automated assembly machine. This panel is comprised of a low cost core material as previously described and is preferably FR4 or similar. The panel further comprises metal pads 1021 on the upper surface which are used to interconnect PV cell terminals to the cover assembly and also to mount other components such as bypass diodes. Surface metallisation 1021 and 1022 is made relatively thick to assist in dissipating heat within the module and, for example, is 2 ounce copper which is approximately 70 microns thick.

Step 2 comprises mounting conventional components such as diodes 1008 onto the circuit panel. Other conventional components such as sensors used to monitor cell performance are also mounted at this time. The process preferably uses standard mounting and fixing means such as reflow soldering or attachment using conductive adhesive.

Step 3 comprises the deposition of a layer of conductive adhesive 1031 or solder paste to the surface of the circuit panel at locations where PV cells are to be mounted. This material is deposited using industry standard techniques such as silk screen or pneumatic dispensing. Step 4 comprises the placement of thermally conductive insulating substrates 1030, with metallised upper surfaces 1032, onto the adhesive or paste regions deposited in step 3. If solder paste is used, the insulating substrate includes a metallised lower surface which the solder will bond to when reflowed. Preferably, the adhesive curing or solder reflow step is performed later in the sequence at the same time as other adhesives are cured or solders are reflowed.

Step 5 comprises deposition of another layer of conductive adhesive or solder paste on top of the metallised surface of the insulating substrates in a similar fashion to step 3.

Step 6 comprises placement of photovoltaic cells 1034 onto the adhesive or solder paste regions deposited in Step 5.

Step 6a (not shown) comprises heating the circuit board panel to cure adhesives or to reflow solder, thereby permanently bonding assembled components together.

Step 7 comprises connecting PV cell terminals to circuit board metallised areas using bond wires 1009. Multiple bond wires are used in parallel to carry the total current of the cell. For example, 20 bond wires may be connected in parallel from each cell terminal. The exact number of bond wires depends on the material (aluminium or gold) and the wire diameter and length. One set of bond wires is attached to contact pads on the upper surface of the cell. The other set is attached to the metal surface of the insulating substrate.

Step 8 comprises attachment of the module cover assemblies 1002. First either conductive adhesive or solder paste 1051 is deposited on metal features of the circuit board which are connected to the cell terminals. Then insulating adhesive 1050 is deposited on the surface of the circuit board around the periphery of each cell module assembly. This insulating adhesive may be applied in liquid form but is preferably an adhesive preform which is rigid in its uncured state. Having deposited the adhesives, cover assemblies 1002 are placed onto the circuit board. The cover assembly preferably has surface features such as cylindrical protrusions which mate with corresponding holes in the circuit boards so that the cover assemblies do not move once placed. The circuit panel preferably is then heated to cure the adhesives and bond the cover assemblies permanently in place. Step 9 comprises filling the cavities in the cover assembly with an optically transparent adhesive 1007. Preferably this adhesive has low viscosity so that it penetrates all regions of the cavity. The adhesive is preferably applied under vacuum to ensure air bubbles are removed. The adhesive preferably a soft material when cured with, for example, a Shore hardness of approximately 30. The purpose of this adhesive is 1) to adhere to and secure the module coverglass which is positioned in Step 10, 2) to maximise optical coupling between the coverglass and the cell by eliminating air gaps and resulting reflections, 3) to provide a high voltage tolerant insulating layer between different connections within the cell module, and 4) to provide an environmental seal for internal cell module components. This adhesive is preferably a silicone based material, for example Dow Corning PV- 1060, although other adhesives such as epoxies can also be used.

Step 10 comprises placing coverglasses 1004 on each cell module. The cover glasses are placed in contact with the liquid adhesive applied in Step 9 and rest on features of the cover assembly 1043 which hold the coverglasses a predetermined distance away from the surface of the PV cells.

Step 10a (not shown) comprises heating the circuit panel to cure the adhesive applied in Step 9, thereby permanently sealing the cell modules.

Step 10b (not shown) comprises separating each cell module by removing the remaining circuit board material that holds each cell module as part of the original circuit board panel. This circuit board material may be removed by punching, or by mechanical or laser cutting processes.

Step 11 comprises attaching interconnection means to each cell module. Interconnections to other CPV panel elements is preferably provided by plastic coated wires 1006 with exposed internal conductor 1026 at the end. These wires are inserted into apertures in each cell module cover as previously described. Preferably, conductive adhesive or solder paste is deposited in each aperture before fitting the wires so that electrical connection is achieved to metallic conductors inside the cover assembly 1053. In addition, an insulating adhesive is applied around the wires when they are inserted. This adhesive is preferably applied as an adhesive preform that is mechanically rigid in its pre-cured state. The preform is preferably a "doughnut" shaped preform the fits around the wire. This insulating adhesive provides the following functions: 1) it secures interconnection wires mechanically to the cell module, 2) it provides a high voltage isolation barrier to internal cell connections and 3) it provides an environmental seal for the internal cell module components.

Step 12 is optional and comprises mounting other structures on each cell module such as optical guiding elements 1011. These elements are preferably mounted using releasable means such as screws 1012, but may also be fixed permanently in place using adhesives. These optical guiding elements are preferably made of reflective material such as metal so as to reflect light that has been inadvertently focused on the cell module cover rather than on the cell. These optical guiding elements thus protect the cell cover assembly from thermal damage. They also reflect stray light in normal operation back onto the cell, thereby increasing conversion efficiency.

Step 13 is also optional and comprises the deposition of a polymer material 1055 on the optical aperture of the cell module. This polymer material is preferably designed to adhere lightly to the coverglass and surrounding surfaces so it can be readily peeled off when the module is put into service. The polymer is thus a peelable adhesive that can be removed without leaving any residue on the coverglass. The polymer layer provides protection for the coverglass and associated anti-reflective coating during shipping and installation of the cell module in a CPV panel. In this way the coverglass is clean when the module is put into service.

Step 14 comprises mounting the cell module in CPV system panel. Removable securing means such as screws or nuts and bolts 1013 are used to secure the modules to the panel housing 1014. The use of removable securing means allows the cell module to be relaced if it becomes faulty.

Step 15 comprises removal of the polymer layer 1055 (if it is used) after the cell module is mounted and interconnected to other panel elements.

Step 16 comprises using the cell module in a concentrating photovoltaic panel to generate electricity. FIGs 1 IA and 1 IB describe an alternate embodiment of a manufacturing sequence of an embodiment relating to a different module cover assembly suited to cassegrain concentrator arrangements. In this manufacturing method, Steps 1 to 7 are the same as described above.

Step 8a comprises attachment of the module cover assemblies 1102. This cover assembly is similar to the cover assembly shown in FIG. 8 except that the upper surface 1160 is curved and has a concave shape to match the shape of a cassegrain primary reflector that is fitted later in the manufacturing sequence. The cover assembly also is shaped to accept tertiary optical elements such as light guides in the region above the cell. These light guides are generally glass or plastic prisms that are tailored to the needs of the system and also provide the coverglass function of the cell module. These prisms are generally placed in the aperture of the cover assembly and are preferably prevented from touching the surfaces of the cover aperture by small raised features 1161. These features ensure that an air gap exists between the guiding structure and cover assembly so that light is guided inside the prism and does not leak out.

As described in Step 8 of FIG. 10, first, either conductive adhesive or solder paste 1151 is deposited on metal features of the circuit board which are connected to the cell terminals. Then insulating adhesive 1150 is deposited on the surface of the circuit board around the periphery of each cell module assembly. This insulating adhesive maybe applied in liquid form but is preferably an adhesive preform which is rigid in its uncured state. Having deposited the adhesives, cover assemblies 1102 are placed onto the circuit board. The cover assembly preferably has surface features such as cylindrical protrusions which mate with corresponding holes in the circuit boards so that the cover assemblies do not move once placed. The circuit panel preferably is then heated to cure the adhesives and bond the cover assemblies permanently in place.

Step 9 A is equivalent to Step 9 of FIG. 10 and comprises filling the cavities in the cover assembly with an optically transparent adhesive 1107. Preferably this adhesive has low viscosity so that it penetrates all regions of the cavity. The adhesive is preferably applied under vacuum to ensure air bubbles are removed. The adhesive preferably a soft material when cured with, for example, a Shore hardness of approximately 30. The purpose of this adhesive is 1) to adhere to and secure the module coverglass which is positioned in Step 10, 2) to maximise optical coupling between the coverglass and the cell by eliminating air gaps and resulting reflections, 3) to provide a high voltage tolerant insulating layer between different connections within the cell module and 4) to provide an environmental seal for internal cell module components. This adhesive is preferably a silicone based material, for example Dow Corning PV-1060, although other adhesives such as epoxies can also be used.

Step 1OA is similar to Step 10 of FIG. 10 and comprises placing optical guiding prisms 1164 on each cell module. The prisms are placed in contact with the liquid adhesive applied in Step 9A and rest on features of the cover assembly 1161 which hold the prisms a predetermined distance away from the surface of the PV cells.

Step 10Aa (not shown) is equivalent to Step 10a of FIG. 10 and comprises heating the circuit panel to cure the adhesive applied in Step 9A, thereby permanently sealing the cell modules.

Step 10Ab (not shown) is equivalent to Step 11 of FIG. 10 and comprises separating each cell module by removing the circuit board material that holds each cell module as part of the original circuit board panel. This circuit board material may be removed by punching, or by mechanical or laser cutting processes.

Step HA is equivalent to Step 11 of FIG. 10 and comprises attaching interconnection means to each cell module. Interconnections to other CPV panel elements is preferably provided by plastic coated wires 1106 with exposed internal conductor 1126 at the end. These wires are inserted into apertures in each cell module cover as previously described. Preferably, conductive adhesive or solder paste is deposited in each aperture before fitting the wires so that electrical connection is achieved to metallic conductors inside the cover assembly 1153. In addition, an insulating adhesive is applied around the wires when they are inserted. This adhesive is preferably applied as an adhesive preform that is mechanically rigid in its pre-cured state. The preform is preferably a "doughnut" shaped preform the fits around the wire. This insulating adhesive provides the following functions: 1) it secures interconnection wires mechanically to the cell module, 2) it provides a high voltage isolation barrier to internal cell connections and 3) it provides an environmental seal for the internal cell module components. Step 12A is equivalent to Step 12 of FIG. 10 and is optional at this stage in the process. This step preferably comprises mounting other structures on each cell module such as the primary cassegrain optical concentrating reflector 1171. These elements are preferably mounted using releasable means such as screws 1112, but may also be fixed permanently in place using adhesives. Alternatively the primary optical reflector may be fitted at a later stage in the manufacturing sequence.

Step 13 A is equivalent to Step 13 of FIG. 10 and is optional at this stage in the process. This step comprises the deposition of a polymer material 1155 on the optical guiding prism of the cell module. This polymer material is preferably designed to adhere lightly to the prism and surrounding surfaces such that it can readily be peeled off when the module is put into service. The polymer is thus a peelable adhesive that can be removed without leaving any residue on the prism. The polymer layer provides protection for the prism and associated anti-reflective coating during shipping and installation of the cell module in a CPV panel. In this way the prism is clean when the module is put into service.

Step 14A is equivalent to Step 14 of FIG. 10 and comprises mounting the cell module in CPV system panel. Removable securing means such as screws or nuts and bolts 1113 are used to secure the modules to the panel housing 1114. The use of removable securing means allows the cell module to be relaced if it becomes faulty.

Step 15A is equivalent to Step 15 of FIG. 10 and comprises removal of the polymer layer 1155 (if it is used) after the cell module is mounted and interconnected to other panel elements.

Step 16A s equivalent to Step 16 of FIG. 10 and comprises using the cell module in a concentrating photovoltaic panel to generate electricity.

To further clarify a manufacturing process, FIG. 12 provides a process flow block diagram according to the manufacturing processes described in FIGs 10 and 11. As previously mentioned, certain process steps may be reordered or omitted. For example, Step 2 comprising mounting of conventional SMT components may be moved to after Step 6 to suit manufacturing processes used to deposit conductive adhesives or solder paste, particularly if silk screen deposition is used and flat circuit board surfaces are needed.

By way of example, a manufacturing process can include the steps:

Step 1 - Loading a circuit board array into automated assembly machine;

Step 2 - Placing conventional SMT components;

Step 3 - Depositing conductive adhesive on each PCB at cell location;

Step 4 - Placing insulating substrates on each PCB at cell location;

Step 5 - Depositing conductive adhesive on each insulating substrate;

Step 6 - Placing PV cells on each insulating substrate and cure adhesives;

Step 7- Connecting cells terminals to PCB with wire bonds;

Step 8 - Selectively depositing conductive and non-conductive adhesives and mount cover assembly;

Step 9 - Filling cover assembly cavity with optically transparent adhesive;

Step 10 - Placing cover-glass in cover assembly aperture and curing adhesive;

Step 10a - Heating circuit panel for curing adhesives;

Step 10b - Cutting PCB array thereby separating each cell module;

Step 11 - Inserting and securing interconnect wires with adhesives;

Step 12 - Mounting additional parts on cell module (optional);

Step 13 - Applying peelable protection film to coverglass (optional);

Step 14 - Mounting cell module on panel housing and terminate connections;

Step 15 - Peeling off protective film; and

Step 16 - Operating Cell module. An advantage of embodiment cell module designs is that they are highly reproducible because of the automated assembly processes used. This means that cell modules are likely to consistently meet stringent standards required from power utility customers.

From yet another perspective, an embodiment provides a means of cleaning cell modules as part of operational maintenance. The inventor has realised that cleaning CPV optical surfaces is particularly challenging. Contaminants deposited on the optical aperture of the cell modules are exposed to intense solar energy which is likely to chemically alter the contaminants such that they burn or oxidise, leaving hard to remove layers on the optical surface. Conventional washing with solvents or detergents are unlikely to remove "baked on" contaminants. The delicate nature of the cell modules' anti reflective coatings means that mechanical scrubbing cannot be used. The inventor has realised that the solution to this problem is to apply a peelable adhesive to the optical surface of the cell module. Preferably the adhesive is applied in a liquid form either as an aerosol spray or as a liquid that is deposited with a soft applicator such as a brush. Preferably, solvents in the adhesive cause soluble contaminants on the surface of the cell module to dissolve into the adhesive, in a direction away from the cell surface. Preferably, on drying, the adhesive is able to be easily peeled off the surface of the cell module, carrying away coarse contaminants such as dust particles embedded in the adhesive layer. In this way the cell module surface can be cleaned without damage to the optical surfaces.

FIG. 13 provides a description of the cleaning method. Cell module 1300 accumulates contaminants 1308 during operational use. A peelable adhesive 1355 is applied to the optical surfaces of the cell module and is allowed to dry forming a pliable layer. This layer is then peeled off the surface as shown in FIG. 13 c, thereby removing contaminants from the optical surfaces of the cell module.

Manufacturing Multi-junction Cells

Referring to FIG. 17, an embodiment provides a metallisation structure for multijunction cells 1700. Substrate 1700 is preferably comprised of germanium and has multijunction cell layers 1701 on the front surface. The uppermost layer 1702 in the multijunction cell structure is a semiconductor layer which has a small bandgap and which readily forms ohmic contacts to metals deposited on its surface. Layer 1702 is preferably InGaAs.

A first metal layer is deposited on top of this small bandgap semiconductor layer. This first metal layer is intended to provide good adhesion to the surface of the semiconductor layer. This first metal layer is either titanium, nickel or chromium, and is preferably titanium. The thickness of this layer is preferably between 100 and 1000 angstroms. On top of the first metal layer is a second metal layer 1704. The intention of this layer is to provide a diffusion barrier which will stop contact metal 1705 from diffusing into the multijunction cell structure. The thickness of this layer is also preferably between 100 and 1000 angstroms. This layer 1704 is chosen to prevent inter-diffusion with contact metal 1705.

In an embodiment, copper is used for a contact layer 1705. Accordingly, titanium nitride is preferably used as the diffusion barrier 1704. By using copper as the interconnect metal layer 1705 three important advantages are obtained: 1) it is a low cost material that is commonly used in the semiconductor industry 2) it can be easily and safely deposited in relatively thick layers by electroplating; 3) it is more closely matched to the thermal expansion characteristics of germanium and GaAs than the conventional metallisation (silver) and 4) it resists corrosion and tarnishing better than silver.

A similar contact structure is also used on the back of the substrate. Because there are no shallow semiconductor junctions on the back of the substrate, there is not problem in using an alloyed ohmic contact. Therefore a thin layer of gold 1706 is preferably deposited on the back surface of the substrate. This layer is preferably between 100 and 1000 angstroms thick. A second metal layer 1707 is deposited on this first layer to improve adhesion. Preferably this layer is either titanium or nickel. A third metal layer

1708 is deposited on top of the second layer to act as a diffusion barrier for contact metal

1709 in a similar manner to the front side contact. This third layer 1708 is preferably titanium nitride and the contact layer 1709 is preferably copper.

Referring to FIG 18A through 18F, an embodiment, by way of example only, further provides a manufacturing sequence for the structure of FIG. 4. Step 1 shows the multijunction wafer used to form cells which comprises a germanium substrate 1801 and multijunction epitaxial structures 1802. The wafer also comprises a low bandgap semiconductor surface layer 1803 to allow non-alloyed contacts to be made to the surface. The surface of this low bandgap layer typically has an oxide layer 1804 on its surface that has formed inadvertently due to exposure with the atmosphere.

Step 2 comprises removal of the surface oxide layer using a wet etching process.

Step 3 comprises the deposition of a surface adhesion layer 1804, which is preferably titanium followed by a diffusion barrier layer 1805 which is preferably titanium nitride.

Step 4 comprises deposition of a photoresist layer 1806 on the front surface. The purpose of this layer is to provide physical protection for the front surface of the wafer while the next step is performed. It is preferably not patterned by lithography.

Step 5 comprises deposition of an alloying contact layer 1807, an adhesion layer

1808, a diffusion barrier layer 1809 and an optional oxidation resistant layer 1810. The alloying contact layer 1807 is preferably gold, the adhesion layer 1808 is preferably titanium or nickel, the diffusion barrier layer 1809 is preferably titanium nitride and the optional oxidation resistant layer 1810 is preferably gold. The thicknesses of each of these layers is preferably between 100 and 1000 angstroms.

Step 6 comprises removal of the photoresist layer 1806.

Step 7 comprises annealing of back contact layer to from an ohmic contact. This process preferably involves the use of rapid thermal annealing (RTA) equipment. The wafer is preferably heated to approximately 400 degrees

Celsius for approximately 30 to 60 seconds.

Step 8 comprises depositing another layer of photoresist 1811 on the front surface of the wafer. This photoresist is chosen for its ability to form narrow deep features when exposed and developed. Industry standard SU-8 photoresist is preferable for this application. It is preferably spun onto the wafer and soft baked to form a layer that is at least 10 microns thick.

Step 9 comprises exposing and developing photoresist 1811 to form recesses 1812.

These recesses preferably have high aspect ratios (i.e. they are deeper than they are wide).

Step 10 comprises deposition of contact metal preferably simultaneously on both the front and back of the wafer. The deposition process is preferably electroplating and the preferred metal is copper. The resulting contact metal fills recesses 1812 in photoresist 1811 to form front side contract fingers 1813 and back side contact 1823.

Step 11 comprises removal of photoresist layer 1811.

Step 12 comprises etching of adhesion layer 1804 and diffusion barrier layer 1805 everywhere on the surface except where they are protected by contact layer 1813. This process forms individual adhesion and diffusion barrier regions 1814 and 1815. Preferably a dry etching process using gaseous etchants is used.

Step 13 comprises a wet etching process that selectively removes ohmic contact layer 1803 except where it is protected by the contact metal 1813 and other metals 1814 and 1815.

Step 14 comprises deposition of photoresist 1818 on the front surface of the wafer.

Step 15 comprises exposing and developing this photoresist to form recesses 1819.

Step 16 comprises an etch process which removes multijunction cell epitaxial layers 1802 in regions where photoresist has been removed. This etching process is preferably a wet etch process.

Step 17 comprises removal of photoresist 1818.

Step 18 comprises deposition of an anti reflective coating layer 1821. This layer may be deposited by evaporation or sputtering techniques. Step 19 comprises deposition of photoresist layer 1822.

Step 20 comprises exposure and development of photoresist layer 1822 to form recesses 1825. The purpose of this layer is to protect the surface of the cell from contamination in the following steps.

Step 21 comprises etching off of the anti-reflective coating in regions where contacts need to be made to front contact metal 1826. This process is done either by wet or dry etching or by laser ablation.

Step 22 comprises dicing of the wafer to form individual cells. Cuts 1827 are preferably made by a laser process.

Step 23 comprises removing photoresist 1822 from the front surface of the cells.

Li an embodiment, a contact metallisation pattern is disclosed which obscures only a small percentage of the active surface of a multijunction cell.

Referring to FIG. 19, a multijunction cell 1901 has front side contact fingers 1903 that radiate from localised contact pads 1902 that are also formed from front contact metal. Each of these contact pads is preferably less than 5% of the total cell area. Four contact pads are shown in FIG. 19. A plurality of pads can be used. Since connections to the multijunction cell are made using bond wires at localised point contact points, the inventor has realised that it is wasteful to place large, non-localised contact regions on the cell surface. In an embodiment relatively small contact pads 1902 are used, with surface contacts 1903 extending from them.

FIG. 19 shows an example of one particular contact pattern. It will be appreciated that alternative patterns are possible. For example fractal patterns may be used. Also regular or irregular, symmetric or asymmetric patterns may be used.

FIG. 20 shows the arrangement of bond wires 2005 according to an embodiment.

Multi-Junction Cells Referring to FIG. 21 A, an embodiment provides a multijunction photovoltaic cell structure comprising Group IV and Group III-V epitaxial photovoltaic subcell layers 2101 and 2106 respectively deposited on an inactive cell substrate 2100. "Inactive" means that the substrate does not contain a photovoltaic junction and provides only a crystal template for growing epitaxial subcell layers and a means of connecting to the lowest subcell.

Conventionally, cell manufacturers utilise a germanium substrate to form the bottom multijunction subcell. The reason for doing this is that the Ge junction is perceived to come for "free" as part of the growth of upper multijunction cell layers. Instead, the inventor has realised that there is a significant cost associated with these conventional Ge subcell layers and a number of significant production and performance advantages can be obtained by forming the lowest bandgap subcell layer epitaxially rather than as part of the substrate.

Presently the cost of an epi-ready germanium substrate is around $80 - $100 (USD). The cost of depositing multijunction cell layers epitaxially on the surface of the substrate is around $55 - $70. This means that around 60% of the cost of the multijunction substrate is associated with the germanium substrate itself. Unlike silicon, germanium is a relatively rare element in the earth's crust and is expensive to extract and refine to semiconductor grade quality. For example, the cost of unrefined germanium is around $1000 per kilogram, or $1 per gram. A 4 inch diameter Ge wafer which is 2150 microns thick therefore contains around $6.50 of unrefined germanium. The difference between this base price and the $80-$100 cost of the epi ready wafer is associated with the purification and physical preparation of the wafer. If the bottom subcell is formed in the substrate, the entire substrate (and the crystal boule it is cut from) has to be produced to exacting standards which are costly. In particular, performance of the germanium subcell is critically dependent on minority carrier lifetimes in the material which need to be maximised for optimal efficiency. This means that impurities in the germanium material need to be reduced to a minimum which increases refining and production costs dramatically. Instead, the inventor realises that it is advantageous to relax the requirements for substrate material quality to lower costs. It is then possible to use the costs saved to form the germanium subcell epitaxially on the surface of the substrate. In forming the germanium junction this way, a much wider choice of subcell parameters is available and the subcells can be produced with high degrees of accuracy (which improves performance) and reproducibility (which increases manufacturing yield and lowers wastage costs).

A second advantage in using an inactive substrate relates to the freedom to choose a "n- on-p" (i.e. p-type substrate) or "p-on-n" structure for the multijunction subcells. In prior art devices comprising Ge junctions formed by diffusion, an n-on-p structure was needed because of the tendency for Group V elements to diffuse into the substrate, thereby doping it n-type. The use of epitaxial techniques to form the bottom subcell allows the freedom to choose dopant polarity such that the minority carrier transport, and hence conversion efficiency, in upper subcells is optimised.

From another perspective, an embodiment provides a multijunction photovoltaic cell structure comprising epitaxial subcell layers made from multiple elements selected from Group IV of the Periodic Table of the Elements.

Although germanium is preferred as the photoactive layer of the bottom subcell in the multijunction cell structure, silicon germanium compound semiconductors may also be used. For example, by introducing 2 percent silicon into the germanium epitaxial layer the lattice constant of the material is reduced so that it exactly matches the lattice constant of GaAs without significantly changing the bandgap. Adding 2 percent silicon to the germanium also helps to stop diffusion between the SiGe layer and adjoining III- V semiconductor layers, thereby forming more abrupt, idealised junctions.

From another perspective, an embodiment provides a multijunction photovoltaic cell structure comprising Group III-V subcells and one or more epitaxial layers made from elements selected from Group FV of the Periodic Table wherein the composition of the Group rv epitaxial layers is changed to alter the lattice constant of the crystal structure between two predefined values and where the lattice constant of Group III-V subcells is fixed and does not change.

Much effort has been invested in the selection of Group III-V materials and bandgaps in prior art multijunction cells. Many proposals have been made regarding the use of metamorphic epitaxial structures and transition layers where Group III-V material compositions are changed during the growth of epitaxial layers to achieve desired subcell bandgap characteristics. However, given the nature of Group M-V semiconductors, such transitions can lead to the formation of crystal defects which act as recombination centres for photo-generated carriers. Although defects can also be created in transition layers formed in Group IV semiconductors, the inventor believes it is advantageous for cell efficiency to restrict the use of transition layers to layers comprising Group FV materials. It will be appreciated that the disclosed cells can have improved crystal quality and higher conversion efficiencies.

In forming the Group III-V subcells, it is advantageous for the inactive substrate surface to have a specific orientation to the crystal planes of the semiconductor. For example, if the substrate is comprised of germanium, it is preferable for the substrate surface to be oriented at between 3 and 9 degrees to the (100) crystal plane.

From another perspective, an embodiment provides a multijunction photovoltaic cell structure comprising first epitaxial subcell layers made from Group FV elements and second epitaxial subcell layers made from Group III and Group V elements, wherein a diffusion barrier layer is deposited between the first and second subcell layers.

Referring to FIG. 2 IB, Group FV subcells 2111 are preferably deposited on inactive substrate 2110. The Group IV subcells comprise a transition layer 2114 which adjusts the crystal lattice constant from one value to another either as a discrete layer on top of the upper Group IV subcell or as one of the subcell layers themselves, for example the emitter layer. An optional diffusion barrier layer 2115 is deposited at the interface between Group IV and Group III-V subcells. This layer may be combined with the transition layer as a single layer.

Unlike conventional multijunction cells where the bottom cell is formed by diffusion of elements into the cell substrate, an embodiment provides improved cell performance and manufacturing reproducibility by minimising diffusion between adjacent subcell layers. Although inter-diffusion can be controlled to some extent by epitaxial growth conditions, an embodiment optionally comprises a diffusion barrier layer between Group IV and Group III-V subcells. The choice of suitable diffusion barriers depends on the materials used in adjacent subcells. For example, silicon or specific compositions of SiGe such as Sio.o ₂ Geo. ₉ g. are suitable in certain circumstances. From another perspective, an embodiment provides a multijunction photovoltaic cell structure comprising a plurality of epitaxial subcell layers made from Group IV elements.

In order to increase cell efficiency above the level currently achieved with triple junction cells, additional subcells need to be added to the multijunction structure. The inventor has realised that it is advantageous to use two subcells formed from Group IV elements to achieve this. An embodiment preferably comprises germanium or a SiGe compound semiconductor incorporating a small percentage of Si (e.g. < 5% Si) as the bottom (or first) subcell of the multijunction cell and SiGe with a higher Si content (e.g. up to 30% Si) as the second subcell deposited on top of the bottom subcell. Most preferably, the second subcell is Si _C nGe _0-83 (i.e. 17% Si 83% Ge). The reason for choosing this particular SiGe composition is that the bandgap of SiGe increases rapidly as the Si percentage increases from 0 to 17% and then increases more slowly. Therefore, a composition of 17% Si provides a relatively large bandgap (0.92eV) with a relatively small crystal lattice offset from germanium (5.619 A compared to 5.658 A for Ge).

Referring to FIG. 21C, bottom subcell 2121 is deposited on inactive substrate 2120. Second subcell 2123 is deposited on top of bottom subcell 2121. A transition layer (not shown in FIG. 21C) is included in either the bottom subcell, the second subcell or in between the subcells to adjust the lattice constant from the bottom cell value to the second cell value. FIG. 21D shows possible locations of transition layers 2132 and 2134 relative to bottom subcell 2131 and second subcell 2133. Optional diffusion barrier layer 2135 is also shown.

Referring now to FIG. 22 A, an embodiment of a 4 junction cell is described. Inactive substrate 2200 is preferably comprised of germanium which is heavily doped to provide low resistivity between front and back surfaces of the substrate. For example the doping concentration is greater than IeI 8. The dopant type (n or p) is chosen to achieve optimal minority carrier transport characteristics in the overall multijunction cell. The impurity concentration of the substrate is relaxed to reduce substrate costs. For example the impurity concentration in the substrate might be at least an order of magnitude higher that conventional "semiconductor grade" germanium substrates. Germanium subcell 2201 is grown on top of the inactive substrate using conventional epitaxial techniques. A small percentage of silicon may be included in the germanium subcell to improve material characteristics or to form subcell junctions. For pure germanium, the lattice constant of this layer is 5.658 angstroms and the bandgap is 0.67eV.

A transition layer 2202 and second subcell 2203 are grown on top of the first subcell. The transition layer is either as a discrete layer positioned on top of the first subcell or is incorporated into the subcell structure of the first or second subcell. The transition layer may be a stepped transition layer where the lattice constant changes abruptly or a graded layer where the lattice constant changes gradually. The material composition of the second subcell is chosen such that it has a larger bandgap than the first subcell. For example, the second subcell maybe Si _o . ₁₇ Geo.s ₃ (i.e. 17% Si 83% Ge) which has a lattice constant of 5.619 angstroms and a bandgap of 0.92eV. Transition layer 2202 is used to adjust the lattice constant from 5.658 to 5.619 angstroms. This transition layer may also be combined with subcell layers such as tunnel junctions or emitter layers of either cell.

A third subcell 2205 is grown on top of the second subcell and has a material composition that provides the same lattice constant as the second cell but a higher bandgap. For example, GaAso. ₈₃ Po.i ₇ has the same lattice constant as the second subcell (5.619A) and bandgap of 1.623eV.

A fourth subcell 2206 is then grown on top of the third subcell in a similar manner. Again, the lattice constant is the same as the subcells below but the bandgap is increased. For example, the fourth subcell may preferably be comprised OfIn _0-4 Ga _0-6 P and have a bandgap of 2.015eV.

Importantly, the thickness of each subcell layer is preferably adjusted to achieve current matching between each of the subcells.

Tunnel junctions are preferably grown between each subcell to achieve series connection of the subcells. Anti reflection coatings are preferably deposited on top of the fourth subcell using conventional techniques to optimise absorption of the cell.

FIG. 22B shows an embodiment of an example 5 junction cell. The subcell layers of this embodiment are equivalent to those of FIG. 22A except that a fifth subcell is introduced between the second and third subcells. This fifth subcell preferably has the same lattice constant as the subcells above and below it and has a bandgap which is larger than the subcell below and smaller than the subcell above. For example this fifth subcell may preferably be comprised of a dilute nitride material such as LiGaAsN, GaAsN with lattice constant 5.619 angstroms and a bandgap of approximately 1.3eV. This fifth subcell may also include elements from groups III or V such as bismuth which act as isoelectronic codopants and improve minority carrier transport characteristics in the subcell.

From another perspective, an embodiment provides a manufacturing method for producing multifunction cells comprising group FV and group III- V semiconductors.

It is known in prior art that there are significant problems associated with growing group IV and group III-V semiconductors in the same growth chamber. For example in MOCVD systems germanium creates a memory effect in growth chambers and is a significant source of contamination. To overcome this problem an embodiment preferably comprises growth of group IV and group III-V materials in separate chambers. To overcome possible surface contamination when substrates are transferred from one growth chamber to another, an embodiment can also comprises the use of an oxide-forming surface layer on the group IV subcell layers which is removed in-situ in the group III-V growth chamber by heating. For example, a the group IV subcell layers may be capped with a Ge layer which oxidises on exposure to the atmosphere to form GeO ₂ . When the substrate is heated in the group III-V growth chamber, this GeO ₂ layer sublimes to leave a clean surface ready for epitaxial growth.

Referring to FIG. 23 A through 23D, the growth process starts with an inactive substrate 2300 onto which group IV subcell layers 2301 are grown. Before the substrate is removed from the growth chamber, an oxidising barrier layer 2307 is formed on the surface of the top subcell. The substrate is then transferred to the group III-V growth chamber and the oxidising barrier layer is removed by heating as shown in FIG. 23B. Group III-V subcells 116 are then deposited onto the surface of the group IV subcells 2301. This sequence is summarised in FIG. 23D.

From another perspective, an embodiment provides a structure and manufacturing method for a multijunction photovoltaic cell comprising an inactive silicon substrate. Many attempts have been made at growing multijunction cell structures on silicon using germanium or germanium compounds such as SiGe as buffer layers. Although some prior art graded buffer techniques provide reasonable substrate crystal quality for the growth of group III-V subcells, a fundamental problem remains: the thermal expansion coefficient of the silicon substrate is much less than the expansion coefficient of the III- V epitaxial layers. This means that significant stress is introduced in the III-V epilayers as substrates are cooled to room temperature after growth.

In an embodiment, a SiGe buffer layer is grown on an inactive silicon substrate. Since the silicon substrate is inactive (i.e. it does not from a photoactive portion of the cell) its material purity can be reduced to lower cost. For example so-called Upgraded Metallurgical Grade (UMG) silicon would be a suitable substrate. The substrate is preferably heavily doped and is used to provide electrical connection to the bottom of the lowest subcell. The polarity of the substrate doping (p or n) is selected to optimise minority carrier transport characteristics in the overall multijunction cell structure.

Preferably, the SiGe buffer layer has either a graded or fixed composition. The top surface of the SiGe layer is preferably predominantly germanium, for example Sio.o ₂ Ge ₀ . ₉₈ , or 100% Ge. The preferred SiGe / Ge buffer layer thickness is less than 1 micron. Because of the significant lattice mismatch between the substrate and buffer layer crystal lattice constants, the SiGe layer as grown will have a large number of defects.

To overcome this problem, ion implantation is first used to create a damaged crystal layer below the surface of the SiGe buffer layer. The substrate is heated during the ion implantation process to minimise damage of the Ge or SiGe surface layer. For example the substrate is preferably heated to around 120 degrees Celsius. After implantation, the substrate is annealed at temperatures between 600 and 1100 degrees Celsius. During the annealing process, the SiGe or Ge surface layer recrystallises starting from the top surface and pushes defects down towards the implant damaged regions which is largely amorphous. As a result, the surface crystal quality is improved and the amorphous damaged layer provides a means of lattice slippage and stress relief as the wafer is cooled from annealing or subsequent growth temperatures. U2009/001350

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US patent 6703293 filed by Tweet et al on 11 My 2002 describes a similar technique for forming SiGe layers on silicon wafers for the purpose of making CMOS integrated circuits. The inventor has realised that this technique can be adapted for use in the unrelated art of multijunction solar cell design and production.

FIG. 24A though 24D show the steps in the manufacturing sequence of a multijunction cell according to an embodiment. Li the first step, a buffer layer 2409 is deposited on an inactive silicon substrate 2400. Then the substrate is heated to a specific temperature, for example 120 degrees Celsius, and then it is implanted with ions such as H, Si or Ge to form an implant damaged buried layer 2408 which is largely amorphous. Then the substrate is annealed at a temperature between 600C and 1 IOOC to recrystallise SiGe or Ge Surface layer 2409 to form surface layer 2419. Then group IV and group IH-V subcells 2401 and 2406 are grown in a manner as described elsewhere in this specification.

Interpretation As noted above, while this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations, uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth.

It would be appreciated that, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.

In alternative embodiments, the one or more processors operate as a standalone device or may be connected, e.g., networked to other processor(s), in a networked deployment, the one or more processors may operate in the capacity of a server or a client machine in server-client network environment, or as a peer machine in a peer-to-peer or distributed network environment.

Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as "processing", "computing", "calculating", "determining" or the like, can refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities into other data similarly represented as physical quantities.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may refer to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that the invention may be embodied in many other forms.