Title:
PIXEL-LEVEL BACKGROUND LIGHT SUBTRACTION
Document Type and Number:
WIPO Patent Application WO/2019/049685
Kind Code:
A1
Abstract:
A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. The pixel circuit 300 includes an overflow gate transistor 304, a photodiode 302, and two taps 310, 312. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract a background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion. Preferably, the pixel circuit 300 further includes a first common node 303, a second common node 305, a CMR transistor 306, and a common supply voltage 308. The overflow gate transistor 304 is connected to the photodiode 302 at the first common node 303 and resets the photodiode 302 globally independent of a normal readout path of the transfer gate. Since the first tap 310 and the second tap 312 share the photodiode 302, only a single overflow gate transistor is used in the pixel circuit 300. The photodiode 302 receives demodulated light 350 and background light 352. Over the course of various time periods, the photodiode 302 provides a charge based on the demodulated light 350 and the background light 352 to the two injection capacitors 326 and 344 and to the two floating diffusion capacitors 322 and 340 for storage and integration. In particular, the two injection capacitors 326 and 344 are used to store the charge from the photodiode 302, which is integrated from a background signal based on the background light 352, when the light source that emits a modulated light is turned off. During the subtraction of the background signal, the charge that is stored by the two injection capacitors 326 and 344 is injected into the corresponding two floating diffusion capacitors 322 and 340 through a serial circuit connection when the two injection switches 324 and 342 are turned on. By alternately turning ON and OFF the two floating diffusion transistors 323 and 341, the two floating diffusion nodes 325 and 343 integrate a combined signal at phases that are opposite to each other.
Inventors:
HANZAWA KATSUHIKO (US)
KANG JINSUK (US)
SEN SELCUK (US)
KANG JINSUK (US)
SEN SELCUK (US)
Application Number:
PCT/JP2018/031285
Publication Date:
March 14, 2019
Filing Date:
August 24, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G01S7/487; G01S7/493
Foreign References:
| EP2996250A1 | 2016-03-16 | |||
| EP2690464A1 | 2014-01-29 | |||
| US20140198183A1 | 2014-07-17 | |||
| US9332200B1 | 2016-05-03 |
Other References:
None
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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