PLANARiZATiON OF A HETEROEPΓΓAXIAL LAYER

FIELD OF THE INVENTION

The present invention relates to the field of heterostructures including a relaxed buffer layer epitaxially grown on a substrate of a different material. More precisely, the invention concerns the polishing techniques which are implemented for such structures either for eliminating the Crosshatch patterns, which occur during growth from the dislocation strain fields, or for smoothing the final surface, after a transfer process has been performed from a donor substrate to a handle substrate.

BACKGROUND OF THE INVENTION

A typical example of heterogeneous structures is the Si(i-X)Ge(X) structure including a relaxed Si(i-X)Ge(χ) buffer layer epitaxially grown on an Si substrate. Such a heterogeneous structure is described in the paper entitled "Planarization of SiGe virtual substrate by CMP and its application to strained Si modulation-doped structures", by K. Sawano et al, published in Journal of Crystal Growth, V251, pp 693-696 (2003). As shown in figure 1, an hetero-structure 100 comprises a strained relaxed Si(i-X)Ge(X) buffer layer 105, which consists of a compositionally step-graded Si(i-X)Ge(X) (x = 0 - 0.3) layer 102 (300 nm) and uniform Si(o.7)Ge(o.3) layer 103 (1 μm), is grown on a p-type Si substrate 101. As a result of the lattice constant mismatch between the substrate and subsequent layers, a relaxation Crosshatch pattern 104 is created at the top surface. Figure 2 shows an image of the surface morphology of a strain-relaxed SiGe buffer layer performed by an atomic force microscope (AFM). The Crosshatch exhibits an initial roughness of 3.2 nm, with a peak-valley of 21.2 nm, for a scan area of 40*40 μm2. Surface variations associated with this Crosshatch pattern must be minimized by appropriate polishing prior to further epitaxy. For example, Si(o.7)Gθ(o.3) buffer layer (100 nm), Si channel layer (15 nm) and Si(o.7)Gθ(o.3) spacer layer (20 nm) can be grown. After this donor wafer is fabricated, a transfer process is performed in order to bond a part of the upper layers from this "engineered" substrate to a handle substrate. An example of such a transfer is the Smart Cut™ technology which is described notably in the article by A. J. Auberton- Herve et al entitled "Why can Smart Cut change the future of microelectronics ?", Int Journal of High Speed Electronics and Systems, Vol. 10, no. 1, 2000, pp 131-146, and implements deep H+ ion implantation so as to create a cleavage zone at the cutting separation. The final top surface, on which damaged zones occurred as a result from the mechanical separation process, has also to be polished in order to get the required smoothness. Lastly, during the recycling of silicon or Si(i-X)Ge(X) donor substrates, polishing processes are implemented to decrease the surface roughness and eliminate the damaged zone of the substrate to be recycled. In this case, the polishing is performed in one or several steps (including a planarization step followed by a finishing step). These three situations are all characterized by a perturbed zone (Crosshatch pattern in the first case, after-breaking residues in the other cases), of a given thickness, existing on a substrate, which has to be eliminated. Works for eliminating Crosshatch patterns and reducing the surface roughness of Si(i-X)Ge(X) substrates have been previously reported by K. Sawano et al. in Journal of Crystal Growth, as mentioned above, and in Material and Science Engineering, in a paper entitled "Surface smoothing of SiGe strain-relaxed buffer layers by chemical mechanical polishing" (B89, pp 406-409, 2002) A roughness of root mean square (RMS) values less than 1 nm (around 0.4 nm over 10*10 μm2 surfaces) after polishing the Si(i-X)Ge(X) substrate is reported. However, the polishing rates achieved for this kind of process are slow, namely a maximum polishing rate of 13 A/sec is obtained. Moreover, the finishing process of a silicon layer of a Si-on-insulator (SOI) material by chemical-mechanical polishing, such as disclosed in the patent FR-A-2 842 755, as well as that for the recycling of a silicon peeled wafer such as disclosed in the patent JP-A-Il 297583, have been already reported. However, they are not appropriate to materials such as SiGe material because the polishing rate is too slow: the Si(i-X)Ge(X) polishing rate is lower by a factor of 5 versus that of Si.

OBJECT AND SUMMARY OF THE INVENTION

In view of such aspects, an object of the present invention is to provide a solution for planarizing disturbed surfaces (Crosshatch patterns, after-cleaving residues) of heteroepitaxial layer materials such as SiGe which permits to increase the polishing rate while reducing the surface roughness in a minimum of time. This object is attained with a method of planarization heteroepitaxial layers comprising a step of chemical-mechanical polishing the surface of the heteroepitaxial layer with a polishing pad having a compressibility comprised between 2 and 15 % and a slurry containing at least 20% of silica particles having a size comprised between 70 and 100 nm. This method allows to reach high polishing rates (ex. 40 A/sec) appropriated for eliminating surface defects on heteroepitaxial layers, such as Crosshatch patterns, and to achieve, in the same time, a final post splitting polish to roughness values less than 0.4 nm RMS, over 10*10 μm2 area, while preserving an industrial, cost effective process. Indeed, the planarization and the smoothing being performed in one-step polishing process, the method of the invention brings cost reduction and production yield in comparison with the usual polishing process which calls for important material removal usually takes place in two steps: one step for planarization followed by a finishing step to get a specified roughness level, such as disclosed in the patent EP 1 016 129. This method of planarization further brings industrial advantages such as good reproducibility and is easily transferable for production. With the method according to the invention, it is possible to remove large thickness of material, about 500 nm for eliminating the Crosshatch pattern and smoothing the surface, or between 50 and 130 nm, for example 80 nm, for the final post splitting polish to smooth the surface of the transferred heteroepitaxial layer. In case of removing Crosshatch pattern from the surface of the heteroepitaxial layer, the parameters of the polishing tool can be adjusted so as to reach a stabilized polishing rate around 40 A/sec, which permits to carry out the step of chemical mechanical polishing for a period less than 200 seconds. For instance, a stabilized polishing rate around 40 A/sec can be reached when the head velocity Vt and the platen velocity Vp of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=46/30 rpm with a polishing pressure P of 6 psi. In the same way, in order to have a polishing rate comprised in the range 35 A/sec to 45 A/sec, the three above parameters can be adjusted according to the following possibilities: - if Vt and Vp are constant (i.e. Vt=46 rpm and Vp=30 rpm) then 5<P<7 psi, - if P and Vp are constant (i.e. P=6 psi and Vp=30 rpm) then 40<Vt<55 rpm, and - if P and Vt are constant (i.e. P=6 psi and Vt=46 rpm) then 25<Vp< 35 rpm. In case of the step of chemical mechanical polishing is carried out after fracture of the heteroepitaxial layer so as to smooth the fractured surface of the layer, the parameters of the polishing tool can be adjusted so as to reach a stabilized polishing rate around 18 A/sec which permits to carry out the chemical mechanical polishing for a period less than 50 seconds. For instance, a stabilized polishing rate around 18 A/sec can be reached when the head velocity Vt and the platen velocity Vp of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=36/30 rpm with a polishing pressure P of 3 psi. In the same way, in order to have a polishing rate comprised in the range 15 A/sec to 25 A/sec, the three above parameters can be adjusted according to the following possibilities: - if Vt and Vp are constant (i.e. Vt=36 rpm and Vp=30 rpm) then 2.5<P<5 psi, - if P and Vp are constant (i.e. P=3 psi and Vp=30 rpm) then 33<Vt<58 rpm, and - if P and Vt are constant (i.e. P=3 psi and Vt=36 rpm) then 18<Vp< 36 rpm.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its advantages will be better understood from the following description, given as non-limiting examples, of preferred embodiments with reference to the appended drawings, in which: - Figure 1 is a schematic cross-sectional view of a typical structure including a relaxed SiGe layer epitaxially grown on a Si substrate; Figure 2 is an image of the surface morphology of a strain- relaxed SiGe buffer layer performed by an atomic force microscope (AFM); - Figure 3 is a schematic of an apparatus for polishing according to an embodiment of the invention; Figures 4A and 4B are curves showing polishing rate variation according to polishing time which are obtained with the method of the invention and with a conventional method; Figure 5 is an AFM image of the surface morphology of a SiGe layer after polishing according to an embodiment of the invention; Figure 6 is a curve showing polishing rate variation according to polishing time in accordance with an embodiment of the invention; Figure 7 is an AFM image of the surface morphology of a SiGe layer after polishing according to an embodiment of the invention;

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Figure 3 illustrates a system 10 according to an embodiment of the invention which can be used for implementing the method of the present invention. The system 10 comprises a polishing head 11 into which a structure 12 to be polished is inserted and a plate 16 covered with a polishing pad 14. A liquid abrasive or slurry is injected into the head, for example via a side conduit 15. A polishing pressure Fe and a movement represented by an arrow 16 are applied to the head 11 to carry out polishing. The structure 12 is a heterostructure comprising at least a heteroepitaxial layer 121, as for example a SiGe layer, which has grown on a substrate 120 of another material such as silicon. The surface of the heteroepitaxial layer 121 is polished in order to eliminate Crosshatch patterns occurred during growth from the dislocation strain fields, or for smoothing the final surface disturbed after a transfer process using a substrate fracture method (ex. Smart Cut™) has been performed (after- cleaving residues). According to the present invention, chemical-mechanical polishing (CMP) is carried out with an intermediate polishing pad, that is a pad having a compressibility rate less than that of a soft pad and more than a hard pad. More precisely, the polishing pad used in the invention has a compressibility rate included between 2% (hard pad) and 15% (soft pad), preferably around 6%. The CMP is also performed by an "aggressive" slurry containing a colloidal solution, such as a NH4OH solution, with high rate of silica, namely more than 20%, and silica particles in 70-100 nm range. The combined use of the above-mentioned intermediate pad and aggressive slurry allows to perform CMP which are suitable to the polishing of heteroepitaxial layers, such as Si^Ge^ layers, permitting, on the one hand, to eliminate either the surface defects (Crosshatch patterns, after-cleaving residues), and, on the other hand, to achieve a final post bonding polish to roughness values less than 0.4 nm RMS, over 10*10 μm2 area, while preserving an industrial, cost effective process. The polishing pad used in the invention is primarily intended for smoothing the surface, while the slurry with a high rate of silica enhances the reactive and mechanical activity of the etching and hence allows to increase the polishing rate for Si(i-X)Ge(X). The advantages of the planarization method of the present invention become apparent when comparing the polishing rate obtained with typical processes used for silicon polishing, such as disclosed in document FR 2 842 755, with that obtained with the planarization method of the invention. Figure 4A shows the polishing rate according to polishing time which is obtained with a typical process (curve B) used for silicon polishing (soft pad of around 10% compressibility, "standard" slurry including a colloidal solution with a low rate of silica (less than 10%) and silica particles of 130-210 nm in diameter), here applied to SiGe polishing, and with the planarization method of the invention (i.e. CMP with intermediate pad stiffness of 6 % compressibility, "aggressive" slurry including at least 20% of silica particles having a size comprised between 70 and 100 nm) (curve A). The results shown in figure 4A are obtained from SiGe samples which consist of Sio.sGeo.2 wafers. Figure 4A clearly shows the advantages of the planarization method of the invention for the polishing rate on Si(i-χ)Ge(X) since it permits to reach a polishing rate of around 40 A/sec, versus 2 A/sec with the typical process. As a result, the processing duration is very short, less than 200 seconds in order to eliminate a Crosshatch pattern of a thickness around 500 nm and prepare surface for bonding. Figure 4B which is an enlarged view of the curve A of figure 4A, indicates that the polishing rate decreases along with time and stabilizes from around 130 seconds to about 40 A/sec, a value well suitable for large materia! removal such as required by Crosshatch pattern removal. Such a stabilization insures also a good process reproducibility. The stabilized polishing rate of 40 A/sec can be obtained by adjusting the parameters of the polishing tool. For instance, a stabilized polishing rate around 40 A/sec can be reached when the Vt, Vp parameters (Vt= head velocity and Vp= platen velocity) of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=46/30 rpm with a polishing pressure P of 6 psi. In the same way, in order to have a polishing rate comprised in the range 35 A/sec to 45 A/sec, the three above parameters can be adjusted according to the following possibilities: - if Vt and Vp are constant (i.e. Vt=46 rpm and Vp=30 rpm) then 5<P<7 psi, - if P and Vp are constant (i.e. P=6 psi and Vp=30 rpm) then 40<Vt<55 rpm, and - if P and Vt are constant (i.e. P=6 psi and Vt=46 rpm) then 25<Vp< 35 rpm. Moreover, this polishing process allows to get roughness levels of Jess than 0.2 nm RMS (over 10*10 μm2 surfaces), as it is apparent from figure 5 which is an AFM image of the surface morphology of a Si(i-X)Ge(X) layer after polishing performed (at a polishing rate of 40 A/sec) for eliminating the Crosshatch pattern and preparing surface for bonding. In case of final polishing after the transfer of the Si(i-X)Ge(X) layer to the insulating substrate, the thickness to be removed, from 50 nm to 130 nm, is much less important than for the Crosshatch elimination, so that the parameters can be adapted in order to get also a good process reproducibility. The corresponding polishing rate variation according to polishing time is shown on figure 6, that is, from around 45 seconds, the polishing rate is stabilized to 18 A/sec. The stabilized polishing rate of 18 A/sec can be obtained by adjusting the parameters of the polishing tool. For instance, a stabilized polishing rate around 18 A/sec can be reached when the Vt, Vp parameters (Vt=head velocity and Vp=platen velocity) of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=36/30 rpm with a polishing pressure P of 3 psi. In the same way, in order to have a polishing rate comprised in the range 15 A/sec to 25 A/sec, the three above parameters can be adjusted according to the following possibilities: - if Vt and Vp are constant (i.e. Vt=36 rpm and Vp=30 rpm) then 2.5<P<5 psi, - if P and Vp are constant (i.e. P=3 psi and Vp=30 rpm) then 33<Vt<58 rpm, and - if P and Vt are constant (i.e. P=3 psi and Vt=36 rpm) then 18<Vp< 36 rpm. After this final polishing, an ultra low level of roughness is achieved, namely 0.19 nm RMS with a peak-valley of 2.1 nm (scan area 10*10 μm2) as shown on figure 7 which is an AFM image of the surface morphology of a Si(i-χ)Ge(X) layer (polished at a polishing rate of 18 A/sec as in figure 6). Such ultra-smooth surfaces are well fitted for applications such as epitaxy regrowth or molecular bonding in view of high end Si-LSI production. To summarize, by using, for polishing heteroepitaxial layers as Si(I-X)Ge(X) layers, more appropriate both pad stiffness grade and silica colloidal solutions, the invention allows to get surface roughness values for as good as a usual final polishing processes, but in a much shorter time. A short time then insures to minimize major defects, such as scratches, which often occur for long polishing times. Consequently, the process is better adapted for mass production. Accordingly also, it is cost effective since performed in a one-step process and limits the related disposable materials.