Title:
POWER FACTOR CORRECTOR WITH HIGH POWER FACTOR AT LOW LOAD OR HIGH MAINS VOLTAGE CONDITIONS
Document Type and Number:
WIPO Patent Application WO/2011/080702
Kind Code:
A3
Abstract:
A power factor corrector raises power factor at low loads or high mains voltages by modifying the switch timing or the current received by the power converter. It achieves this by increasing the switch -on time of a control switch during the falling time so that the majority of the switch -on time during a mains period occurs during the falling time, to thereby control the current received by the converter to compensate for current received by the intermediate filter. Some embodiments may employ a feedback system to produce one or more error signals that modify the control signal used to control the operation of the converter. Various embodiments may also include additional stages that limit the compensation range of the error signal.
Inventors:
HALBERSTADT HANS (NL)
Application Number:
PCT/IB2010/056097
Publication Date:
August 25, 2011
Filing Date:
December 28, 2010
Export Citation:
Assignee:
NXP BV (NL)
HALBERSTADT HANS (NL)
HALBERSTADT HANS (NL)
International Classes:
H02M1/42
Foreign References:
| US20080246444A1 | 2008-10-09 | |||
| US7295452B1 | 2007-11-13 |
Other References:
KIM J W ET AL: "Variable On-time Control of the Critical Conduction Mode Boost Power Factor Correction Converter to Improve Zero-crossing Distortion", POWER ELECTRONICS AND DRIVES SYSTEMS, 2005. PEDS 2005. INTERNATIONAL C ONFERENCE ON KUALA LUMPUR, MALAYSIA 28-01 NOV. 2005, PISCATAWAY, NJ, USA,IEEE, vol. 2, 28 November 2005 (2005-11-28), pages 1542 - 1546, XP010909892, ISBN: 978-0-7803-9296-0, DOI: DOI:10.1109/PEDS.2005.1619933
LAI J-S ET AL: "Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode", PROCEEDINGS OF THE ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC). SAN DIEGO, MAR. 7 - 11, 1993; [PROCEEDINGS OF THE ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC)], NEW YORK, IEEE, US, vol. CONF. 8, 7 March 1993 (1993-03-07), pages 267 - 273, XP010111214, ISBN: 978-0-7803-0983-8, DOI: DOI:10.1109/APEC.1993.290621
LAI J-S ET AL: "Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode", PROCEEDINGS OF THE ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC). SAN DIEGO, MAR. 7 - 11, 1993; [PROCEEDINGS OF THE ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC)], NEW YORK, IEEE, US, vol. CONF. 8, 7 March 1993 (1993-03-07), pages 267 - 273, XP010111214, ISBN: 978-0-7803-0983-8, DOI: DOI:10.1109/APEC.1993.290621
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