Related Applications

[0001] This application claims the benefit of provisional patent application serial number 63/114,193, filed November 16, 2020, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management circuit, and particularly an envelope tracking (ET) power management circuit.

Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires higher data rates offered by wireless communication technologies, such as fifth-generation new-radio (5G- NR) technology configured to communicate a millimeter wave (mmWave) radio frequency (RF) signal(s) in an mmWave spectrum located above 12 GHz frequency. To achieve the higher data rates, a mobile communication device may employ a power amplifier(s) to increase output power of the mmWave RF signal(s) (e.g., maintaining sufficient energy per bit). However, the increased output power of mmWave RF signal(s) can lead to increased power consumption and thermal dissipation in the mobile communication device, thus compromising overall performance and user experiences. [0005] Envelope tracking (ET) is a power management technology designed to improve efficiency of the power amplifier(s) to help reduce power consumption and thermal dissipation in the mobile communication device. The power amplifier(s) is typically configured to amplify the mmWave RF signal(s) based on an ET voltage(s). As the name suggests, the ET voltage(s) is generated in accordance with a time-variant power envelope(s) of the mmWave RF signal(s) being amplified by the power amplifier(s). Understandably, the better the ET voltage(s) tracks the time-variant power envelope(s) of the mmWave RF signal(s), the better ET performance and higher efficiency can be achieved at the power amplifier(s). Given that the time-variant power envelope(s) of the mmWave RF signal(s) can vary rapidly between peaks and bottoms, the ET voltage(s) must be adjusted swiftly based on an instantaneous power level of the mmWave RF signal(s) to maintain temporal alignment with the time-variant power envelope(s) at the power amplifier(s).

[0006] Embodiments of the disclosure relate to a power management circuit operable with multiple supply voltages. In embodiments disclosed herein, the power management circuit includes a supply voltage ci rcuit(s) capable of simultaneously generating multiple supply voltages at different voltage levels. The power management circuit also includes multiple envelope tracking (ET) voltage circuits each configured to generate a respective one of multiple ET voltages based on the multiple supply voltages. In this regard, each ET voltage circuit can dynamically use different supply voltages from time to time to generate the respective ET voltage. As a result, it is possible to prevent distortion (e.g., amplitude clipping) in any of the ET voltages, especially when large peak-to-average ratio (PAR) is expected in the ET voltages.

[0007] In one aspect, a power management circuit is provided. The power management circuit includes an ET integrated circuit (ETIC). The ETIC includes a supply voltage circuit configured to generate multiple supply voltages at multiple voltage levels, respectively. The ETIC also includes multiple ET voltage circuits each configured to generate a respective one of multiple of ET voltages based on the multiple supply voltages and a respective one of multiple target voltages.

[0008] In another aspect, a power management circuit is provided. The power management circuit includes a distributed ETIC. The distributed ETIC includes a distributed supply voltage circuit coupled to an ETIC and is configured to generate multiple distributed supply voltages based on a selected supply voltage received from the ETIC. The distributed ETIC also includes at least one distributed ET voltage circuit configured to generate at least one distributed ET voltage based on the multiple distributed supply voltages and at least one distributed target voltage.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1 is a schematic diagram of an exemplary power management circuit configured according to embodiments of the present disclosure to operate based on multiple supply voltages;

[0012] Figure 2 is a schematic diagram providing an exemplary illustration of a supply voltage circuit in the power management circuit of Figure 1 to generate the multiple supply voltages;

[0013] Figure 3A is a schematic diagram providing an exemplary illustration of an envelope tracking (ET) integrated circuit (ETIC) in the power management circuit of Figure 1 configured to generate an ET voltage(s) based on all of the supply voltages; [0014] Figure 3B is a schematic diagram of an exemplary voltage selection circuit, which can be provided in the ETIC in Figure 3A to dynamically select any of the supply voltages;

[0015] Figure 4A is a schematic diagram providing an exemplary illustration of an ETIC in the power management circuit of Figure 1 configured to generate an ET voltage(s) based on a subset of the supply voltages; and

[0016] Figure 4B is a schematic diagram of an exemplary voltage selection circuit, which can be provided in the ETIC in Figure 4A to dynamically select any supply voltage from the subset of the supply voltages.

Detailed Description

[0017] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0018] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0019] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0023] Embodiments of the disclosure relate to a power management circuit operable with multiple supply voltages. In embodiments disclosed herein, the power management circuit includes a supply voltage ci rcuit(s) capable of simultaneously generating multiple supply voltages at different voltage levels. The power management circuit also includes multiple envelope tracking (ET) voltage circuits each configured to generate a respective one of multiple ET voltages based on the multiple supply voltages. In this regard, each ET voltage circuit can dynamically use different supply voltages from time to time to generate the respective ET voltage. As a result, it is possible to prevent distortion (e.g., amplitude clipping) in any of the ET voltages, especially when large peak-to-average ratio (PAR) is expected in the ET voltages.

[0024] Figure 1 is a schematic diagram of an exemplary power management circuit 10 configured according to embodiments of the present disclosure to operate based on multiple supply voltages VSU PI -VSU PN. The power management circuit 10 includes an ET integrated circuit (ETIC) 12 and a distributed ETIC 14 (denoted as “DETIC”). Herein, the ETIC 12 and the distributed ETIC 14 are separate circuits coupled via a voltage line 16. In a nonlimiting example, the ETIC 12 and the distributed ETIC 14 can be provided at different locations (e.g., top edge and bottom edge) of an electric device (e.g., smartphone).

[0025] The ETIC 12 is configured to include a supply voltage circuit 18. The supply voltage circuit 18 is configured to simultaneously generate the supply voltages VSU PI -VSU PN at different voltage levels. The ETIC 12 also includes multiple ET voltage circuits 20A and 20B, each configured to generate a respective one of multiple ET voltages VCCA and VCCB at a respective one of multiple voltage outputs 22A and 22B based on a respective one of multiple target voltages VTGTA and VTGTB.

[0026] In embodiments disclosed herein, the ET voltage circuit 20A is configured to generate the ET voltage VCCA based on at least a subset (VSU PA) of the supply voltages VSUPI-VSUPN (VSUPA C {VSUPI-VSUPN}). Likewise, the ET voltage circuit 20B is configured to generate the ET voltage VCCB based on at least a subset (VSUPB) of the supply voltages VSUPI-VSUPN (VSUPB C {VSUPI-VSUPN}). Accordingly, each of the ET voltage circuits 20A and 20B can dynamically select an appropriate one of the supply voltages VSUPI-VSUPN with required headroom based on the respective one of the target voltages VTGTA and VTGTB. AS a result, it is possible to prevent distortion (e.g., amplitude clipping) in any of the ET voltages VCCA and VCCB, especially when a large PAR is expected in the ET voltages VCCA and VCCB.

[0027] In a non-limiting example, the supply voltage circuit 18 can be configured to generate a high supply voltage VSUPH, a first medium supply voltage VSUPMI , a second medium supply voltage VSUPM2, and a low supply voltage VSUPL at different volage levels (VSUPH + VSUPMI + VSUPM ₂ + VSUPL). The first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL can be determined based on the high supply voltage VSUPH in accordance with equation (Eq. 1 ) below.

VSUPMI = VSUPH * (1 - X) / (1 + X) (Eq. 1 ) VSUPM2 = VSUPH * x / (1 + x) VSUPL = VSUPH / (1 + x)

[0028] In the equation (Eq. 1 ) above, x represents a scaling factor (0 < x < 1 ). For example, the scaling factor x can equal to 0, , ¹ /2, %, or 1 . Figure 2 is a schematic diagram providing an exemplary illustration of the supply voltage circuit 18 in the ETIC 12 of the power management circuit 10 of Figure 1 .

Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0029] The supply voltage circuit 18 includes a multi-level charge pump (MCP) 24. The MCP 24 is configured to generate a direct current (DC) voltage VDC based on a battery voltage VBAT. In a non-limiting example, the MCP 24 can be a buck-boost circuit configured to operate in a buck mode to generate the DC voltage VDC as being less than or equal to the battery voltage VBAT or in a boost mode to generate the DC voltage VDC as being greater than the battery voltage VBAT.

[0030] The supply voltage circuit 18 may include a controller 26, which can be a pulse width modulation (PWM) controller for example, configured to control the MCP 24. Specifically, the controller 26 may control the MCP 24 to operate in the buck mode and the boost mode based on a first control signal 28 and a second control signal 30, respectively. By alternating the first control signal 28 and the second control signal 30, it is possible to cause the MCP 24 to generate the DC voltage VDC in accordance with a specific duty cycle. In a non-limiting example, the controller 26 can determine the specific duty cycle based on a maximum target voltage VTGT-MAX, which is determined based on a higher one of the target voltages VTGTA and VTGTB (VTGT-MAX = MAX (VTGTA, VTGTB)).

[0031] The MCP 24 is coupled to an inductor-capacitor (LC) circuit 32, which includes a power inductor 34 and a power capacitor 36. The LC circuit 32 is configured to output an average of the DC voltage VDC (referred herein as “average DC voltage VAVG”) at a coupling node 38 based on the specific duty cycle. In an embodiment, the supply voltage circuit 18 can be configured to directly output the average DC voltage VAVG as the high supply voltage VSUPH. [0032] The supply voltage circuit 18 also includes a capacitor-based voltage circuit 40 (denoted as “pCBB”), which is coupled to the coupling node 38. In an embodiment, the capacitor-based voltage circuit 40 is configured to generate the first medium supply voltage VSU PMI , the second medium supply voltage VSU PM2, and the low supply voltage VSUPL as a function of the high supply voltage VSU PH in accordance with the equation (Eq. 1 ) above.

[0033] The controller 26 may be further configured to receive a feedback of the high supply voltage VSU PH. Accordingly, the controller 26 may adjust the specific duty cycle of the MCP 24 based on both the maximum target voltage VTGT-MAX and the feedback of the high supply voltage VSU PH. It should be appreciated that it is also possible for the controller 26 to receive feedback of the first medium supply voltage VSU PMI , the second medium supply voltage VSUPM2, or the low supply voltage VSUPL given the fact that the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL are all derived from the high supply voltage VSUPH.

[0034] As previously discussed in Figure 1 , the ET voltage circuit 20A is configured to generate the ET voltage VCCA based on at least a subset (VSUPA) of the supply voltages VSUPI-VSUPN (VSUPA C {VSUPI-VSUPN}). Likewise, the ET voltage circuit 20B is configured to generate the ET voltage VCCB based on at least a subset (VSUPB) of the supply voltages VSUPI-VSUPN (VSUPB C {VSUPI-VSUPN}). In one embodiment, the subset VSUPA and the subset VSUPB can each include all of the supply voltages VSUPI-VSUPN.

[0035] In this regard, in a non-limiting example, each of the ET voltage circuits 20A and 20B in the ETIC 12 can be configured to receive all of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. Accordingly, the ET voltage circuits 20A and 20B can each generate the respective one of the ET voltages VCCA and VCCB based on any of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL.

[0036] Figure 3A is a schematic diagram providing an exemplary illustration of the ETIC 12 in Figure 1 configured to generate each of the ET voltages VCCA and VCCB based on all of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. Common elements between Figures 1 and 3A are shown therein with common element numbers and will not be re-described herein.

[0037] The ET voltage circuits 20A and 20B each include a respective one of multiple voltage amplifiers VAA and VAB, a respective one of multiple offset capacitors COFFA and COFFB, and a respective one of multiple feedback loops FBA and FBB. The voltage amplifiers VAA and VAB are each configured to generate a respective one of multiple initial ET voltages VAMPA and VAMPB based on a respective one of the target voltages VTGTA and VTGTB. The offset capacitors COFFA and COFFB are each configured to raise a respective one of the initial ET voltages VAMPA and VAMPB by a respective one of multiple offset voltages VOFFA and VOFFB to generate a respective one of the ET voltages VCCA and VCCB at a respective one of the voltage outputs 22A and 22B. The feedback loops FBA and FBB are each configured to provide feedback of a respective one of the ET voltages VCCA and VCCB to a respective one of the voltage amplifiers VAA and VAB. In this regard, the ET voltage circuits 20A and 20B are both closed-loop ET circuits.

[0038] In an embodiment, the voltage amplifiers VAA and VAB are both configured to operate based on any of the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. AS such, the supply voltage circuit 18 is configured to provide all of the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL to both the ET voltage circuits 20A and 20B.

[0039] The ET voltage circuits 20A and 20B are each configured to include a respective one of multiple voltage selection circuits 42A (denoted as “VSELA”) and 42B (denoted as “VSELB”). The voltage selection circuits 42A and 42B are each coupled to the supply voltage circuit 18 to receive the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. Accordingly, the voltage selection circuits 42A and 42B are each configured to dynamically provide any one of the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL to a respective one of the voltage amplifiers VAA and VAB. More specifically, the voltage selection circuit 42A can dynamically select a supply voltage VSUPA from the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL and provide the supply voltage VSUPA to the voltage amplifier VAA. Similarly, the voltage selection circuit 42B can dynamically select a supply voltage VSUPB from the high supply voltage VSUPH, the first medium supply voltage VSUPM-I , the second medium supply voltage VSU PM2, and the low supply voltage VSU PL and provide the supply voltage VSU PB to the voltage amplifier VAB.

[0040] Figure 3B is a schematic diagram of an exemplary voltage selection circuit 44, which can be provided in the ETIC 12 in Figure 3A as any of the voltage selection circuits 42A and 42B. Common elements between Figures 3A and 3B are shown therein with common element numbers and will not be redescribed herein.

[0041] In a non-limiting example, the voltage selection circuit 44 includes a voltage controller 46 and multiple selection transistors 48(1 )-48(4) (e.g., p-type or n-type field-effect transistors). Each of the selection transistors 48(1 )-48(4) has a respective one of multiple first electrodes 50(1 )-50(4) (e.g., collector electrode or drain electrode) configured to receive a respective one of multiple input voltages VIN-I -VIN-4. Herein, the input voltages VIN-I-VIN-4 are equivalent to the high supply voltage VSU PH, the first medium supply voltage VSU PMI , the second medium supply voltage VSUPM2, and the low supply voltage VSU PL, respectively.

[0042] Each of the selection transistors 48(1 )-48(4) has a respective one of multiple second electrodes 52(1 )-52(4) (e.g., emitter electrode or source electrode) coupled to an output node 54 to output any one of the input voltages VIN-I -VIN-4 as an output voltage VOUT. Herein, the output voltage VOUT is equivalent to the supply voltage VSU PA when the voltage selection circuit 44 is provided in the ET voltage circuit 20A as the voltage selection circuit 42A or the supply voltage VSUPB when the voltage selection circuit 44 is provided in the ET voltage circuit 20B as the voltage selection circuit 42B.

[0043] Each of the selection transistors 48(1 )-48(4) has a respective one of multiple third electrodes 56(1 )-56(4) (e.g., base electrode or gate electrode) coupled to the voltage controller 46. The voltage controller 46 is configured to receive a target voltage VTGT, which can be the target voltage VTGTA when the voltage selection circuit 44 is provided in the ET voltage circuit 20A as the voltage selection circuit 42A or the target voltage VTGTB when the voltage selection circuit 44 is provided in the ET voltage circuit 20B as the voltage selection circuit 42B. [0044] The voltage controller 46 is configured to dynamically determine, based on the target voltage VTGT, which of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL should be selected as the output voltage VOUT. Accordingly, the voltage controller 46 can assert a respective one of multiple bias voltages VBI-VB4 above a respective threshold voltage on a respective one of the third electrodes 56(1 )-56(4) to thereby cause a respective one of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL to be outputted at the output node 54.

[0045] As previously discussed in Figure 1 , the ET voltage circuit 20A is configured to generate the ET voltage VCCA based on at least a subset (VSUPA) of the supply voltages VSUPI-VSUPN (VSUPA C {VSUPI-VSUPN}). Likewise, the ET voltage circuit 20B is configured to generate the ET voltage VCCB based on at least a subset (VSUPB) of the supply voltages VSUPI-VSUPN (VSUPB C {VSUPI-VSUPN}). In one embodiment, the subset VSUPA and the subset VSUPB can each include a subset the supply voltages VSUPI-VSUPN.

[0046] In this regard, in a non-limiting example, each of the ET voltage circuits 20A and 20B in the ETIC 12 can be configured to receive a subset of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. Accordingly, the ET voltage circuits 20A and 20B can each generate the respective one of the ET voltages VCCA and VCCB based on a respective subset of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL.

[0047] Figure 4A is a schematic diagram providing an exemplary illustration of the ETIC 12 in Figure 1 configured to generate each of the ET voltages VCCA and VCCB based on a respective subset of the high supply voltage VSUPH, the first medium supply voltage VSUPMI , the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. Common elements between Figures 1 , 3A, and 4A are shown therein with common element numbers and will not be redescribed herein.

[0048] In an embodiment, the voltage amplifier VAA may be configured to operate based on the high supply voltage VSUPH, the first medium supply voltage VSUPMI, and the voltage amplifier VAB may be configured to operate based on the second medium supply voltage VSUPM2, and the low supply voltage VSUPL. AS such, the supply voltage circuit 18 is configured to provide the high supply voltage VSUPH and the first medium supply voltage VSUPMI to the ET voltage circuit 20A and provide the second medium supply voltage VSUPM2 and the low supply voltage VSUPL to the ET voltage circuit 20B.

[0049] The ET voltage circuits 20A and 20B are each configured to include a respective one of multiple voltage selection circuits 58A (denoted as “VSELA”) and 58B (denoted as “VSELB”). The voltage selection circuits 58A and 58B are each coupled to the supply voltage circuit 18. The voltage selection circuit 58A receives the high supply voltage VSUPH and the first medium supply voltage VSUPMI, and the voltage selection circuit 58B receives the second medium supply voltage VSUPM2 and the low supply voltage VSUPL. Accordingly, the voltage selection circuit 58A is configured to dynamically provide any one of the high supply voltage VSUPH and the first medium supply voltage VSUPMI to the voltage amplifier VAA as the supply voltage VSUPA. Similarly, the voltage selection circuit 58B is configured to dynamically provide any one of the second medium supply voltage VSUPM2 and the low supply voltage VSUPL to the voltage amplifier VAB as the supply voltage VSUPB.

[0050] Figure 4B is a schematic diagram of an exemplary voltage selection circuit 60, which can be provided in the ETIC 12 in Figure 4A as any of the voltage selection circuits 58A and 58B. Common elements between Figures 4A and 4B are shown therein with common element numbers and will not be redescribed herein.

[0051] In a non-limiting example, the voltage selection circuit 60 includes a voltage controller 62 and a pair of selection transistors 64(1 )-64(2) (e.g., p-type or n-type field-effect transistors). Each of the selection transistors 64(1 )-64(2) has a respective one of multiple first electrodes 66(1)-66(2) (e.g., collector electrode or drain electrode) configured to receive a respective one of a pair of input voltages VIN-I-VIN-2. Herein, the input voltages VIN-I-VIN-2 are equivalent to the high supply voltage VSU PH and the first medium supply voltage VSU PMI when the voltage selection circuit 60 is provided in the ET voltage circuit 20A as the voltage selection circuit 58A. Alternatively, the input voltages VIN-I-VIN-2 are equivalent to the second medium supply voltage VSU PM2, and the low supply voltage VSU PL when the voltage selection circuit 60 is provided in the ET voltage circuit 20B as the voltage selection circuit 58B.

[0052] Each of the selection transistors 64(1 )-64(2) has a respective one of multiple second electrodes 68(1 )-68(2) (e.g., emitter electrode or source electrode) coupled to an output node 70 to output any one of the input voltages VIN-I -VIN-2 as an output voltage VOUT. Herein, the output voltage VOUT selects the supply voltage VSUPA when the voltage selection circuit 60 is provided in the ET voltage circuit 20A as the voltage selection circuit 58A or the supply voltage VSU PB when the voltage selection circuit 60 is provided in the ET voltage circuit 20B as the voltage selection circuit 58B.

[0053] Each of the selection transistors 64(1 )-64(2) has a respective one of multiple third electrodes 72(1 )-72(2) (e.g., base electrode or gate electrode) coupled to the voltage controller 62. The voltage controller 62 is configured to receive a target voltage VTGT, which can be the target voltage VTGTA when the voltage selection circuit 60 is provided in the ET voltage circuit 20A as the voltage selection circuit 58A or the target voltage VTGTB when the voltage selection circuit 60 is provided in the ET voltage circuit 20B as the voltage selection circuit 58B.

[0054] The voltage controller 62 is configured to dynamically determine, based on the target voltage VTGT, which of the input voltages VIN-I-VIN-2 should be selected as the output voltage VOUT. Accordingly, the voltage controller 62 can assert a respective one of multiple bias voltages VBI -VB2 above a respective threshold voltage on a respective one of the third electrodes 72(1 )-72(2)) to thereby cause a respective one of input voltages VIN-I-VIN-2 to be outputted at the output node 70.

[0055] With reference back to Figure 1 , the distributed ETIC 14 can be configured to include a distributed supply voltage circuit 74. The distributed supply voltage circuit 74 is configured to simultaneously generate multiple distributed supply voltages DVSUPI-DVSUPN at different voltage levels based on a selected supply voltage VSUPx (1 < X < N) of the plurality of supply voltages VSUPI-VSUPN. The distributed ETIC 14 also includes at least one distributed ET voltage circuit 76. The distributed ET voltage circuit 76 is configured to generate at least one distributed ET voltage DVcc in at least one distributed voltage output 78 based on at least one distributed target voltage DVTGT.

[0056] In embodiments disclosed herein, the distributed ET voltage circuit 76 is configured to generate the distributed ET voltage DVcc based on at least a subset (VSUPD) of the distributed supply voltages DVSUPI-DVSUPN (VSUPD C {DVSUPI-DVSUPN}). Accordingly, the distributed ET voltage circuit 76 can dynamically select an appropriate one of the distributed supply voltages DVSUPI-DVSUPN with required headroom based on the distributed target voltage DVTGT. AS a result, it is possible to prevent distortion (e.g., amplitude clipping) in the distributed ET voltage DVcc, especially when a large PAR is expected in the distributed ET voltage DVcc.

[0057] In a non-limiting example, the supply voltage circuit 18 in the ETIC 12 can be configured to generate a high supply voltage VSUPH, a first medium supply voltage VSUPM-I, a second medium supply voltage VSUPM2, and a low supply voltage VSUPL at different volage levels (VSUPH + VSUPMI + VSUPM2 + VSUPL). In this regard, in a non-limiting example, the distributed supply voltage circuit 74 can receive the low supply voltage VSUPL from the supply voltage circuit 18 as the selected supply voltage VSUPx. Accordingly, the distributed supply voltage circuit 74 may be configured to generate the distributed supply voltages DVSUPI-DVSUPN to include a distributed high supply voltage DVSUPH (e.g., DVSUPi), a distributed first medium supply voltage DVSUPMI (e.g., DVSUP2), a distributed second medium supply voltage DVSUPM2 (e.g., DVSUPN- 1), and a distributed low supply voltage DVSUPL (e.g., DVSUPN) at different volage levels (DVSUPH + DVSUPMI + DVSUPM2 + DVSUPL) as a function of the selected supply voltage VSUPx.

[0058] For example, the distributed low supply voltage DVSUPL, the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI, and the distributed second medium supply voltage DVSUPM2 can be determined based on the selected supply voltage VSUPx in accordance with equation (Eq. 2) below.

DVSUPL = VSUPx (Eq. 2)

DVSUPH = DVSUPL * (1 + y) DVSUPMI = DVSUPL * (1 - y) DVSUPM2 = DVSUPL * y

[0059] In the equation (Eq. 2) above, y represents a distributed scaling factor (0 < y < 1 ), which can be identical or different from the scaling factor x used by the supply voltage circuit 18 in the ETIC 12. In a non-limiting example, the distributed supply voltage circuit 74 can be implemented based on a similar configuration as the supply voltage circuit 18 in Figure 2.

[0060] The distributed ET voltage circuit 76 includes a distributed voltage amplifier DVA, a distributed offset capacitor DCOFF, and a distributed feedback loop DFB. The distributed voltage amplifier DVA is configured to generate a distributed initial ET voltage DVAMP based on a distributed target voltage DVTGT and a selected distributed supply voltage DVSUP among the distributed supply voltages DVSUPI-DVSUPN. The distributed offset capacitor DCOFF is configured to raise the distributed initial ET voltage DVAMP by a distributed offset voltage DVOFF to generate the distributed ET voltage DVcc at the distributed voltage output 78. The distributed feedback loop DFB is configured to provide feedback of the distributed ET voltages DVcc to the distributed voltage amplifier DVA. In this regard, the distributed ET voltage circuit 76 is also a closed-loop ET circuit. [0061] In an embodiment, the distributed voltage amplifier DVA can be configured to operate based on any of the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL. AS such, the distributed supply voltage circuit 74 is configured to provide all of the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL to the distributed ET voltage circuit 76.

[0062] The distributed ET voltage circuit 76 is thus configured to include a distributed voltage selection circuit 80 (denoted as “DVSEL”). The distributed voltage selection circuit 80 is coupled to the distributed supply voltage circuit 74 to receive the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL. Accordingly, the distributed voltage selection circuit 80 is configured to dynamically provide any one of the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL to the distributed voltage amplifier DVA as the selected distributed supply voltage DVSUP. In this regard, the distributed voltage selection circuit 80 can be implemented in accordance with the voltage selection circuit 44 as in Figure 3B.

[0063] In another embodiment, the distributed voltage amplifier DVA can be configured to operate based on a subset of the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL. AS such, the distributed supply voltage circuit 74 is configured to provide a subset of the distributed high supply voltage DVSUPH, the distributed first medium supply voltage DVSUPMI , the distributed second medium supply voltage DVSUPM2, and the distributed low supply voltage DVSUPL to the distributed ET voltage circuit 76 as the selected distributed supply voltage DVSUP. In this regard, the distributed voltage selection circuit 80 may be implemented in accordance with the voltage selection circuit 60 as in Figure 4B.

[0064] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.