Related Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63/397,025, filed on August 11 , 2022, the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The technology of the disclosure relates generally to a power management circuit capable of supporting both envelope tracking (ET) and average power tracking (APT) operations.

Background

[0003] Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] A fifth-generation new radio (5G-NR) wireless communication system is widely regarded as a technological advancement that can achieve significantly higher data throughput, improved coverage range, enhanced signaling efficiency, and reduced latency compared to the existing third-generation (3G) and fourthgeneration (4G) communication systems. A 5G-NR mobile communication device usually transmits and receives a radio frequency (RF) signal(s) in a millimeter wave (mmWave) RF spectrum that is typically above 6 GHz. Notably, the RF signal(s) transmitted in the mmWave RF spectrum may be more susceptible to propagation attenuation and interference that can result in substantial reduction in data throughput. To help mitigate propagation attenuation and maintain desirable data throughput, the 5G-NR mobile communication device employs a power amplifier(s) to amplify the RF signal(s) before transmitting in the mm Wave RF spectrum.

[0005] Envelope tracking (ET) and average power tracking (APT) are power management techniques designed to improve operating efficiency of the power amplifier(s). Specifically, the power amplifier(s) is configured to amplify the RF signal(s) based on a modulated voltage (ET modulated or APT modulated) that closely tracks a time-variant power envelope of the RF signal(s). The modulated voltage is typically generated by a power management integrated circuit (PMIC) that is typically separated from the power amplifier(s). As such, it is possible that the modulated voltage can become misaligned in phase and/or amplitude from the time-variant power envelope of the RF signal(s) to potentially distort the RF signal at the power amplifier(s). As such, it is desirable to align the modulated voltage with the time-variant power envelope of the RF signal(s), both in phase and amplitude, at the power amplifier(s).

Summary

[0006] Embodiments of the disclosure relate to a power management circuit. Herein, a transceiver circuit is configured to generate a modulated differential signal that includes information related to a time-variant amplitude of a radio frequency (RF) signal. Accordingly, a power management integrated circuit (PMIC) can generate a modulated voltage, a modulated phase correction voltage, and a modulated amplitude correction voltage based on the modulated differential signal. The modulated voltage is provided to a power amplifier circuit for amplifying the RF signal, and the modulated phase correction voltage and the modulated amplitude correction voltage are provided to a power amplifier circuit to cause phase and amplitude adjustment in the RF signal. By performing phase and amplitude adjustment in the RF signal, it is possible to ensure proper alignment between the modulated voltage and the time-variant amplitude of the RF signal to thereby avoid potential distortion in the RF signal.

[0007] In one aspect, a power management circuit is provided. The power management circuit includes a transceiver circuit. The transceiver circuit is configured to generate a digital signal having a time-variant amplitude. The transceiver circuit is also configured to convert the digital signal into an RF signal associated with the time-variant amplitude. The transceiver circuit is also configured to generate a modulated differential signal based on the time-variant amplitude. The power management circuit also includes a PMIC. The PMIC is configured to generate a modulated voltage, a modulated amplitude correction voltage, and a modulated phase correction voltage based on the modulated differential signal.

[0008] In another aspect, a transceiver circuit is provided. The transceiver circuit includes a first signal processing circuit. The first signal processing circuit is configured to generate a digital signal having a time-variant amplitude. The first signal processing circuit is also configured to convert the digital signal into an RF signal associated with the time-variant amplitude. The transceiver circuit also includes a second signal processing circuit. The second signal processing circuit is configured to generate a modulated differential signal based on the timevariant amplitude.

[0009] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

Brief Description of the Drawing Figures

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] Figure 1 is a schematic diagram of an exemplary power management circuit that can be configured according to various embodiments of the present disclosure to align a modulated voltage with a time-variant amplitude of a radio frequency (RF) signal at a power amplifier circuit; [0012] Figure 2 is a schematic diagram providing an exemplary illustration of the power management circuit of Figure 1 configured according to one embodiment of the present disclosure;

[0013] Figure 3 is a schematic diagram providing an exemplary illustration of a digital differential signal generated according to the embodiment of Figure 2; [0014] Figure 4 is a schematic diagram providing an exemplary illustration of the power management circuit of Figure 1 configured according to another embodiment of the present disclosure;

[0015] Figure 5 is a schematic diagram providing an exemplary illustration of a digital differential signal generated according to the embodiment of Figure 4;

[0016] Figure 6 is a schematic diagram providing an exemplary illustration of the power management circuit of Figure 1 configured according to another embodiment of the present disclosure;

[0017] Figure 7 is a schematic diagram providing an exemplary illustration of a digital differential signal generated according to the embodiment of Figure 6; and

[0018] Figure 8 is a schematic diagram of an exemplary user element wherein the power management circuits of Figures 2, 4, and 6 can be provided.

Detailed Description

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0022] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Embodiments of the disclosure relate to a power management circuit. Herein, a transceiver circuit is configured to generate a modulated differential signal that includes information related to a time-variant amplitude of a radio frequency (RF) signal. Accordingly, a power management integrated circuit (PMIC) can generate a modulated voltage, a modulated phase correction voltage, and a modulated amplitude correction voltage based on the modulated differential signal. The modulated voltage is provided to a power amplifier circuit for amplifying the RF signal, and the modulated phase correction voltage and the modulated amplitude correction voltage are provided to a power amplifier circuit to cause phase and amplitude adjustment in the RF signal. By performing phase and amplitude adjustment in the RF signal, it is possible to ensure proper alignment between the modulated voltage and the time-variant amplitude of the RF signal to thereby avoid potential distortion in the RF signal.

[0026] Figure 1 is a schematic diagram of an exemplary power management circuit 10 that can be configured according to various embodiments of the present disclosure to align a modulated voltage Vcc with a time-variant amplitude Vl ² +Q ² of an RF signal 12 at a power amplifier circuit 14. The power management circuit 10 further includes a transceiver circuit 16 and a PMIC 18, both are separated from the power amplifier circuit 14 and each other. The transceiver circuit 16 is configured to generate the RF signal 12 associated with the time-variant amplitude Vl ² +Q ² and provide the RF signal 12 to the power amplifier circuit 14.

[0027] The transceiver circuit 16 is further configured to generate a modulated differential signal SDIFF based on the time-variant amplitude Vl ² +Q ² of the RF signal 12 and provide the modulated differential signal SDIFF to the PMIC 18. As discussed in detail below, the modulated differential signal SDIFF can be generated based on various embodiments of the present disclosure to include such information that enables the PMIC 18 to generate a modulated phase correction voltage \/<p and a modulated amplitude voltage VAM, in addition to the modulated voltage Vcc. The modulated phase correction voltage V^ and the modulated amplitude voltage VAM can be provided to the power amplifier circuit 14 to cause phase and amplitude correction in the RF signal 12 such that the time-variant amplitude Vl ² +Q ² of the RF signal 12 can be properly aligned with the modulated voltage Vcc at the power amplifier circuit 14. As a result, it is possible to prevent potential distortion (e.g., amplitude clipping) in the RF signal 12 when the RF signal 12 is amplified at the power amplifier circuit 14.

[0028] Figure 2 is a schematic diagram providing an exemplary illustration of a power management circuit 10A configured according to one embodiment of the present disclosure. Common elements between Figures 1 and 2 are shown therein with common element numbers and will not be re-described herein.

[0029] Herein, the power management circuit 10A includes a transceiver circuit 16A and a PMIC 18A that are functionally equivalent to the transceiver circuit 16 and the PMIC 18 in Figure 1. The power amplifier circuit 14 includes a phase shifter circuit 20, a driver stage amplifier 22, and an output stage amplifier 24. The phase shifter circuit 20 is configured to perform phase correction on the RF signal 12 based on the modulated phase correction voltage \/<p to generate a phase-adjusted RF signal 26. The driver stage amplifier 22 is coupled to the phase shifter circuit 20. The driver stage amplifier 22 first performs an amplitude adjustment on the phase-adjusted RF signal 26 based on the modulated amplitude correction voltage VAM to generate a phase-amplitude-adjusted RF signal 28 and then amplifies the phase-amplitude-adjusted RF signal 28 based on the modulated voltage Vcc. The output stage amplifier 24 is coupled to the driver stage amplifier 22 and configured to further amplify the phase-amplitude- adjusted RF signal 28 based on the modulated voltage Vcc.

[0030] According to an embodiment of the present disclosure, the transceiver circuit 16A includes a first signal processing circuit 29 that includes a digital processing circuit 30. The transceiver circuit 16A also includes a second signal processing circuit 31 A, which includes a first filter circuit 32, a first envelope detector 34, a phase correction lookup table (LUT) circuit 36, a second filter circuit 38, a second envelope detector 40, an amplitude correction LUT circuit 42, a combiner 44, a voltage LUT circuit 46, a modulator circuit 48, and a digital to analog converter (DAC) 50. The first signal processing circuit 29 further includes a signal processing circuit 52. The digital processing circuit 30 is configured to generate a digital signal 54 associated with the time-variant amplitude Vl ² +Q ² . The signal processing circuit 52 is configured to convert the digital signal 54 into the RF signal 12, which understandably is also associated with the time variant amplitude l ² +Q ² , and provide the RF signal 12 to the phase shifter circuit 20 in the power amplifier circuit 14. In a non-limiting example, the signal processing circuit 52 can include additional active/passive circuits (e.g., DAC, frequency converter, etc.), which are omitted herein for the sake of simplicity.

[0031] The first filter circuit 32 is configured to apply a first complex filter HAPT(S) to the digital signal 54 to generate a first equalized digital signal 56. The first envelope detector 34 is configured to detect the time-variant amplitude l ² +Q ² of the first equalized digital signal 56. The phase correction LUT circuit 36 may include an isophase LUT (not shown) and is configured to generate the modulated phase correction voltage \/<p based on the detected time-variant amplitude l ² +Q ² of the first equalized digital signal 56.

[0032] The second filter circuit 38 is configured to apply a second complex filter HET(S) to the digital signal 54 to generate a second equalized digital signal 58. The second envelope detector 40 is configured to detect the time-variant amplitude l ² +Q ² of the second equalized digital signal 58. The amplitude correction LUT circuit 42 may include an isogain LUT (not shown) and is configured to generate the modulated amplitude correction voltage VAM based on the detected time-variant amplitude Vl ² +Q ² of the second equalized digital signal 58. The combiner 44 is configured to combine the modulated phase correction voltage and the modulated amplitude correction voltage VAM to generate a modulated phase-amplitude correction voltage V^-AM.

[0033] The voltage LUT circuit 46 may include a voltage LUT (not shown) and is configured to generate a modulated target voltage VCC-TGT based on the detected time-variant amplitude l ² +Q ² of the second equalized digital signal 58. In one embodiment, the modulated target voltage VCC-TGT can be an envelope tracking (ET) modulated target voltage for generating the modulated voltage Vcc as an ET modulated voltage. In another embodiment, the modulated target voltage VCC-TGT can be an average power tracking (APT) modulated target voltage for generating the modulated voltage Vcc as an APT modulated voltage. The modulator circuit 48 is configured to generate a digital differential signal DDIFF that includes the modulated phase-amplitude correction voltage V^-AM and the modulated target voltage VCC-TGT. The DAC 50 is configured to convert the digital differential signal DDIFF into the modulated differential signal SDIFF.

[0034] Figure 3 is a schematic diagram providing an exemplary illustration of the digital differential signal DDIFF generated according to the embodiment of Figure 2. Common elements between Figures 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0035] Herein, the modulator circuit 48 further includes a first modulator 60 and a second modulator 62. The first modulator 60 is configured to generate a first digital differential signal DDIFF-I of the digital differential signal DDIFF and the second modulator 62 is configured to generate a second digital differential signal DDIFF-2 of the digital differential signal DDIFF. Specifically, the first modulator 60 generates the first digital differential signal DDIFF-I by adding one-half ( ¹ Z) of the modulated target voltage VCC-TGT to the modulated phase-amplitude correction voltage V^-AM (DDIFF-I = V^-AM + ^VCC-TGT). The second modulator 62 generates the second digital differential signal DDIFF-2 by subtracting one-half (T ) of the modulated target voltage VCC-TGT from the modulated phase-amplitude correction voltage AM (DDIFF-2 = V^-AM - ^VCC-TGT). In other words, the digital differential signal DDIFF includes a common signal (a.k.a. the modulated phase-amplitude correction voltage V^-AM) and a differential signal (a.k.a. the modulated target voltage VCC-TGT).

[0036] With reference back to Figure 2, the PMIC 18A can include a voltage modulation circuit 64 and a splitter circuit 66. The voltage modulation circuit 64 is configured to extract the modulated target voltage VCC-TGT from the modulated differential signal SDIFF and generate the modulated voltage Vcc based on the modulated target voltage CC-TGT. The splitter circuit 66 is configured to extract the modulated phase-amplitude correction voltage V^-AM from the modulated differential signal SDIFF and split the modulated phase-amplitude correction voltage V^-AM into the modulated phase correction voltage \/<p and the modulated amplitude correction voltage VAM.

[0037] Figure 4 is a schematic diagram providing an exemplary illustration of a power management circuit 10B configured according to another embodiment of the present disclosure. Common elements between Figures 1 , 2, and 4 are shown therein with common element numbers and will not be re-described herein.

[0038] Herein, the power management circuit 10B includes a transceiver circuit 16B and a PMIC 18B that are functionally equivalent to the transceiver circuit 16 and the PMIC 18 in Figure 1. According to an embodiment of the present disclosure, the transceiver circuit 16B includes a second signal processing circuit 31 B, which includes a filter circuit 68, an envelope detector 70, a voltage LUT circuit 72, and a modulator circuit 74. The filter circuit 68 is configured to apply a complex filter HET(S) to the digital signal 54 to generate an equalized digital signal 76. The envelope detector 70 is configured to detect the time-variant amplitude Vl ² +Q ² of the equalized digital signal 76. The voltage LUT circuit 72 may include a voltage LUT (not shown) and is configured to generate the modulated target voltage VCC-TGT based on the detected time-variant amplitude Vl ² +Q ² of the equalized digital signal 76. The voltage LUT circuit 72 may be coupled to the voltage modulation circuit 64 via an RF frontend (RFFE) interface to thereby provide the modulated target voltage VCC-TGT to the voltage modulation circuit 64. The modulator circuit 74 is configured to generate a digital differential signal DDIFF that includes the time-variant amplitude l ² +Q ² of the equalized digital signal 76 and the modulated target voltage VCC-TGT.

[0039] Figure 5 is a schematic diagram providing an exemplary illustration of the digital differential signal DDIFF generated according to the embodiment of Figure 4. Common elements between Figures 4 and 5 are shown therein with common element numbers and will not be re-described herein.

[0040] Herein, the modulator circuit 74 further includes a first modulator 78 and a second modulator 80. The first modulator 78 is configured to generate a first digital differential signal DDIFF-I of the digital differential signal DDIFF and the second modulator 80 is configured to generate a second digital differential signal DDIFF-2 of the digital differential signal DDIFF. Specifically, the first modulator 78 generates the first digital differential signal DDIFF-I by adding one-half ( ¹ Z) of the modulated target voltage VCC-TGT to the time-variant amplitude Vl ² +Q ² of the equalized digital signal 76 (DDIFF-I = Vl ² +Q ² + VCC-TGT). The second modulator 80 generates the second digital differential signal DDIFF-2 by subtracting one-half (%) of the modulated target voltage VCC-TGT from the time-variant amplitude l ² +Q ² of the equalized digital signal 76 (DDIFF-2 = l ² +Q ² - ^VCC-TGT). In other words, the digital differential signal DDIFF includes a common signal (a.k.a. the time-variant amplitude Vl ² +Q ² of the equalized digital signal 76) and a differential signal (a.k.a. the modulated target voltage VCC-TGT).

[0041] With reference back to Figure 4, the PMIC 18B can include the voltage modulation circuit 64, the phase correction LUT circuit 36, and the amplitude correction LUT circuit 42. The voltage modulation circuit 64 is configured to generate the modulated voltage Vcc based on the modulated target voltage VCC- TGT. The phase correction LUT circuit 36 is configured to extract the time-variant amplitude Vl ² +Q ² from the modulated differential signal SDIFF and generate the modulated phase correction voltage . The amplitude correction LUT circuit 42 is configured to extract the time-variant amplitude Vl ² +Q ² from the modulated differential signal SDIFF and generate the modulated amplitude correction voltage VAM.

[0042] Figure 6 is a schematic diagram providing an exemplary illustration of a power management circuit 10C configured according to one embodiment of the present disclosure. Common elements between Figures 1 , 2, and 6 are shown therein with common element numbers and will not be re-described herein.

[0043] Herein, the power management circuit 10C includes a transceiver circuit 16C that is functionally equivalent to the transceiver circuit 16 in Figure 1 . In an embodiment, the transceiver circuit 16C includes a second signal processing circuit 31 C. Herein, the phase correction LUT circuit 36 and the amplitude correction LUT circuit 42 are configured to provide the modulated phase correction voltage \/<p and the modulated amplitude correction voltage AM to a modulator 82 that generates the modulated differential signal SDIFF. The voltage LUT circuit 46 is configured to provide the modulated target voltage Vcc- TGT to the voltage modulation circuit 64 for generating the modulated voltage Vcc. [0044] Figure 7 is a schematic diagram providing an exemplary illustration of the digital differential signal DDIFF generated according to the embodiment of Figure 6. Common elements between Figures 6 and 7 are shown therein with common element numbers and will not be re-described herein.

[0045] Herein, the modulator circuit 82 further includes a first modulator 84 and a second modulator 86. The first modulator 84 is configured to generate a first digital differential signal DDIFF-I of the digital differential signal DDIFF and the second modulator 86 is configured to generate a second digital differential signal DDIFF-2 of the digital differential signal DDIFF. Specifically, the first modulator 84 generates the first digital differential signal DDIFF-I by adding the modulated amplitude correction voltage VAM to the modulated phase correction voltage \ <p and (DDIFF-I = \/<p + VAM). The second modulator 86 generates the second digital differential signal DDIFF-2 by subtracting the modulated amplitude correction voltage VAM from the modulated amplitude correction voltage VAM (DDIFF-2 = \f<p - VAM). In other words, the digital differential signal DDIFF includes a common signal (a.k.a. the modulated phase correction voltage V^) and a differential signal (a.k.a. the modulated amplitude correction voltage VAM).

[0046] The power management circuit 10A of Figure 2, the power management circuit 10B of Figure 4, and the power management circuit 10C of Figure 6 can be provided in a user element to enable bandwidth adaptation according to embodiments described above. In this regard, Figure 8 is a schematic diagram of an exemplary user element 100 wherein the power management circuit 10A of Figure 2, the power management circuit 10B of Figure 4, and the power management circuit 10C of Figure 6 can be provided. [0047] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0048] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0049] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art. [0050] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.