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Title:
REDUCE DCO FREQUENCY OVERLAP-INDUCED LIMIT CYCLE IN HYBRID AND DIGITAL PLLS
Document Type and Number:
WIPO Patent Application WO/2024/036322
Kind Code:
A3
Abstract:
An apparatus comprising: a digital integrator to generate a frequency error signal at least partially based on a digital phase error signal; and a logic circuit to set an integrated value of the digital phase error signal stored at a register of the digital integrator.

Inventors:
FOUZAR YOUCEF (CA)
EL-HALWAGY WALEED (CA)
ROBERTS WILLIAM (US)
KSHONZE KRISTOPHER (CA)
WARSALEE FAIZAL (CA)
Application Number:
PCT/US2023/072107
Publication Date:
April 25, 2024
Filing Date:
August 11, 2023
Export Citation:
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Assignee:
MICROCHIP TECH INC (US)
International Classes:
H03L7/093; H03L7/099
Foreign References:
US20150263848A12015-09-17
US20100039183A12010-02-18
US20220077864A12022-03-10
US20130027098A12013-01-31
CN114142854A2022-03-04
US20090309666A12009-12-17
Other References:
VO TUAN MINH: "A Non-Overlapping Frequency Aid Technique for Fractional-N Digital Bang-Bang PLLs", 2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), IEEE, 11 November 2019 (2019-11-11), pages 1 - 4, XP033687721, DOI: 10.1109/APCCAS47518.2019.8953127
CHAO PEI-YING ET AL: "Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 21, no. 12, 1 December 2013 (2013-12-01), pages 2240 - 2249, XP011530549, ISSN: 1063-8210, [retrieved on 20131014], DOI: 10.1109/TVLSI.2012.2230454
Attorney, Agent or Firm:
BACA, Andrew, J. et al. (US)
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