Title

A reference voltage circuit

Field of the Invention The present invention relates to a reference voltage circuit which provides a reference voltage with reduced dependencies on semiconductor process variations.

Background Voltage reference circuits for providing constant voltage references or temperature dependent voltage references are well known in the art. Typically these circuits are provided as bandgap circuits which are designed to operably sum two voltages with opposite temperature slopes so as to provide the output reference voltage. One of the voltages is a Complementary-To-Absolute Temperature (CTAT) voltage typically provided by a base-emitter voltage of a forward biased bipolar transistor whose response is temperature dependent and reduces with increasing temperatures. The other is a Proportional-To-Absolute Temperature (PTAT) voltage which may be typically derived from the base- emitter voltage differences of two bipolar transistors operating at different collector current densities. As a PTAT voltage it will be understood that the output voltage will increase in relation to increasing temperatures. When the summed PTAT voltage and the CTAT voltage are balanced together the voltage is at a first order temperature insensitive. While being advantageous in providing reliable reference voltages and very common within the art, voltage reference circuits provided by traditional bandgap reference voltage circuits are sensitive to semiconductor process variations.

An example of a prior art bandgap reference voltage circuit 100 is illustrated in Figure 1. This circuit is exemplary of the type of prior art circuitry which is sensitive to process variations. Disadvantages associated with such process

variation sensitivities include the fact that the reference voltage generated may vary from process to process, lot to lot and even from die to die in the same wafer. This is obviously not a satisfactory arrangement.

The bandgap reference voltage circuit 100 of Figure 1 includes a first PNP bipolar transistor Qi operating at a first collector current density and a second PNP bipolar transistor Q ₂ operating at a second collector current density which is less than that of the first collector current density. The emitter of the first bipolar transistor Qi is coupled to the inverting input of an operational amplifier A and the emitter of the second bipolar transistor Q ₂ is coupled via a resistor n to the non-inverting input of the amplifier A. A third bipolar transistor Q ₃ is coupled to a reference voltage node ref via a second resistor r ₂ . The collector current density difference between Qi and Q ₂ may be established by having the emitter area of the second bipolar transistor Q ₂ larger than the emitter area of the first bipolar transistor Qi . Alternatively multiple transistors may be provided in each leg, with the sum of the collector currents of each of the transistors in a first leg being greater than that in a second leg. As a consequence of the differences in collector current densities between the bipolar transistors Qi and Q ₂ a base-emitter voltage difference (δV _be ) is developed across the resistor n.

kT T

AV _be = —\n(n) = AV _be (T _o y - (1) q T ₀

Where: k is the Boltzmann constant; q is the charge on the electron, T is operating temperature in Kelvin,

T ₀ is reference temperature, usually room temperature, δVbe(To) is base-emitter voltage difference at T ₀ , n is the collector current density ratio of Qi and Q ₂ .

This voltage difference (δV _be ) is of the form of a proportional to absolute temperature (PTAT) voltage. The voltage at the non-inverting input of the amplifier A is related to the base-emitter voltage difference (δV _be ), and as a consequence the amplifier A forces the voltage at the inverting input to be equal to the voltage at the non-inverting input. The output of the amplifier A drives the gates of three PMOS transistors MPi, MP ₂ , and MP ₃ which are arranged to mirror the PTAT current which flows through n such that the drain current of the three PMOS transistors are PTAT.

/ - ^δ ^ - ^δ ^ ( ^γO ) * ^γ ₍ 2)

P T* rx ^r x ^T o

The drain current of MP ₃ flows through r ₂ resulting in a PTAT (δV _be ) voltage across r ₂ . The voltage at the reference voltage node ref is the summation of the base-emitter voltage (CTAT) of the bipolar transistor Q ₃ and the base emitter voltage difference δV _be voltage (PTAT) developed across r ₂ due to the PTAT current from MP ₃ .

V _ref = V _be (03) + I _PTAT * T ₂ = V _be (03) + AV _be0 *l- *^ (3)

T ₀ r _x

It is clear from equation 3 that the reference voltage at node ref has a base- emitter V _be component and a base emitter voltage difference δV _be component. The V _be component is inherently temperature dependent and is also subject to semiconductor process dependencies. Thus, the reference voltage may vary significantly from process to process, lot to lot and even from die to die in the same wafer.

The base-emitter voltage temperature dependence is given by equation 4:

KST) = V _G0 -(V _G0 -V _be (T ₀ )y?--m * — *lnA + — *H— ) (4)

T ₀ q T ₀ q j _c0

Where:

V _GO is an extrapolated bandgap voltage from T ₀ to OK, Vbe(To) is the base-emitter voltage at T ₀ , m is a temperature constant, typically denoted as XTI in computer simulation programs, jc is collector current density at actual temperature, T, and jco is collector current density at T ₀ .

The first two terms of equation 4 correspond to a linear variation against temperature and the last two terms correspond to a non-linear variation, usually denoted as curvature voltage V _cur v-

V _cun = -m * — * lnλ + — * H-) (5) q T _{0 q} j _c0

The reference voltage temperature dependence based on equations 3, 4 and 5 is given by equation 6:

K _ef = V _G0 - (V _G0 - V _be (T ₀ ) - AV _be0 *í ^r ) * L + V _curv (6) r\ ¹ O To cancel the linear terms in equation 6 it is necessary to arrange that the following condition is met:

V _G0 = V _be (T ₀ ) + AV _be0 ^ (7)

Then the reference voltage value corresponds to the extrapolated bandgap voltage, V _G o plus a small curvature term, V _CU rv- One of the main disadvantages of this circuit design is that the reference voltage value corresponds to an unknown parameter, V _G o, of about 1.1V to 1.22V, with large variation from process to process, lot to lot and even from die to die in the same wafer. This variation is translated into a large spread of the resultant reference voltage values and also of its Thermal Coefficient (TC). In order to compensate for this variation large trimming ranges are required to achieve both the desired absolute value output from the circuit and also to maintain its TC within desired operating parameters.

There is therefore a need to provide a voltage reference circuit which provides a reference voltage which has less dependency on semiconductor process variations compared to traditional bandgap based reference voltage circuits.

Summary

These and other problems are addressed by providing a bandgap reference voltage circuit which provides a reference voltage which is based on a PTAT voltage which is substantially less process dependent than a base emitter voltage V _be . Such a reference voltage circuit may be implemented using an amplifier, a first load element, and a feedback load element. First and second PTAT currents and a CTAT current are arranged such that the generated reference voltage provided at the output of the amplifier is based on a PTAT base-emitter voltage difference δV _be

These and other features will be better understood with reference to the followings Figures which are provided to assist in an understanding of the teaching of the invention.

Brief Description Of The Drawings The present application will now be described with reference to the accompanying drawings in which:

Figure 1 is a schematic circuit diagram of a prior art bandgap voltage reference circuit.

Figure 2 is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention.

Figure 3 is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention.

Figure 4 is a graph showing the simulated reference voltage of the circuit of Figure 2 against temperature.

Figure 5 is a schematic circuit diagram of a circuit provided in accordance with the teaching of the present invention.

Figure 6 is a graph showing the simulated reference voltage of the circuit of Figure 5 against temperature.

Detailed Description of the Drawings

The invention will now be described with reference to some exemplary reference voltage circuits which are provided to assist in an understanding of the teaching of the invention. It will be understood that these circuits are provided to assist in an understanding of benefits that are derivable from following the teaching of the invention and are not to be construed as limiting in any fashion. Furthermore, circuit elements or components that are described with reference to any one Figure may be interchanged with those of other Figures or other equivalent circuit elements without departing from the spirit of the present invention.

Referring to the drawings and initially to Figure 2 there is illustrated a reference voltage circuit 200 which provides a reference voltage based on a PTAT base- emitter voltage difference δV _be rather than the extrapolated bandgap voltage V _GO By removing the dependency of the reference voltage to this extrapolated bandgap parameter, such a circuit experiences less process dependencies compared to traditional bandgap voltage reference circuits. The reference voltage circuit 200 comprises an operational amplifier A having an inverting input, non-inverting input and an output. A first load element, namely, resistor r ₃ , is coupled between the non-inverting input of the operational amplifier A and a ground node gnd. A feedback load element, namely resistor r ₄ , is coupled between the inverting input and the output of the amplifier A.

A current biasing circuit arranged between a power supply V _dd and the ground node gnd provides first and second PTAT currents l_PTATi and l_PTAT ₂ and a CTAT current I_CTAT. It will be appreciated that such while referred to in the singular that the current biasing circuit could include individual circuit elements each being configured to generate a specific one of the required PTAT or CTAT currents. In this embodiment, the generated PTAT currents, l_PTATi and I_PTAT ₂ , are substantially equal. It will however, be appreciated by those skilled in the art that the individual PTAT currents, l_PTATi and I_PTAT ₂ , may be of different values. The first PTAT current l_PTATi flows from V _dc ι to ground through the resistor r ₃ which results in a corresponding PTAT voltage being developed across r ₃ .

The CTAT current I_CTAT sums with the second PTAT current I_PTAT ₂ at a summation node common to inverting input of the amplifier A, and the feedback path including the resistor r ₄ . As the CTAT current I_CTAT is of opposite polarity to the second PTAT current I_PTAT ₂ , the resultant current provided at the summation node is a combination of the CTAT element, I_CTAT, subtracted from the PTAT element, I_PTAT ₂ .

By suitably generating the values of the CTAT element, I_CTAT, and the second PTAT element, I_PTAT ₂ , it is possible to generate at a first predetermined temperature a combination of these two currents that will effectively cancel each other out. The resultant current at this predetermined temperature will be zero. While this first predetermined temperature T ₀ , may be chosen to have any temperature value, in this exemplary arrangement, the first predetermined temperature is taken to be room temperature, typically taken to be 25° Celsius but it will be understood that the specific temperature taken is not important in this context.

In operation, the first PTAT current l_PTATi ( a positive current) flows through r ₃ resulting in a PTAT voltage dropped across r ₃ . The CTAT current I_CTAT is a negative current, and the second PTAT current I_PTAT ₂ is a positive current. Thus, at the summation node I_CTAT subtracts from I_PTAT ₂ which results in zero current at the summation node at room temperature T ₀ . Therefore at room temperature, no current flows through the feedback resistor r ₄ .

At a second predetermined temperature, Ti, preferably higher than room temperature, T ₀ , the feedback resistor r ₄ is set such that the reference voltage remains as it was at the first temperature T ₀ . The output voltage of amplifier A which is the reference voltage for the circuit, corresponds to the voltage applied at the non-inverting input of amplifier A (which is the voltage drop across resistor r3) minus the voltage drop across r4 due to the current difference between I_PTAT ₂ and I_CTAT. However, at room temperature the current difference between I_PTAT ₂ and I_CTAT is zero. Thus, the output of the amplifier A is related to the PTAT voltage dropped across r ₃ resulting from I_PTAT ₂ flowing through r ₃ . As this is of a PTAT form, it will have a temperature dependency such that the voltage measured at the output of the amplifier can be related to the operating conditions of the circuit.

Referring now to Figure 3 there is illustrated another reference voltage circuit 300 provided in accordance with the teaching of the present invention. This circuit includes examples of the type of circuit elements that may be used to generate the PTAT and CTAT currents of Figure 2 again provides a reference voltage based on a PTAT base-emitter voltage difference δV _be rather than the extrapolated bandgap voltage V _G o- In this way and similarly to the circuit of Figure 2, the reference voltage output from the circuit of Figure 3 suffers from less process dependencies compared to traditional bandgap voltage reference.

The reference voltage circuit 300 is substantially similar to the reference voltage circuit 200. The amplifier A, and the resistors r ₃ and r ₄ operate in substantially

the same manner as described with reference to Figure 2. Additionally, the resistor r ₄ is shown has having an explicit trimming element r ₄ _ _trιm which may be trimmed for varying the resistance of r ₄ .

In this arrangement of Figure 3, specifics of the current biasing circuit that was described with reference to Figure 2 are shown. In this exemplary arrangement of how such a circuit could be provided, the circuit includes a PTAT current generator which provides the first and second PTAT currents l_PTATi and I_PTAT ₂ , and a CTAT current generator which provides the CTAT current I_CTAT. The PTAT current generator comprises a first PNP bipolar transistor Qi which has its emitter coupled to the non-inverting input of a second operational amplifier (op-amp) Ai,and a second PNP bipolar transistor, Q ₂ , which has its emitter coupled to the inverting input of the op-amp Ai via a load element, namely, sense resistor The base and collectors of both the first and second bipolar transistors Qi, Q ₂ are coupled to the ground node gnd. The emitter area of the second bipolar transistor Q ₂ is a constant "n" times larger than the emitter area of the first bipolar transistor Qi such that the collector current density of the first bipolar transistor Qi is greater than the collector current density of the second bipolar transistor Q ₂ . As was described above with reference to a typical known bandgap reference voltage circuit such differences in collector current density may be achieved in any one of a number of different ways and it is not intended to limit the teaching of the present invention to any one specific arrangement. The sense resistor r1 includes a trimming element ri trim which may be trimmed for varying the resistance of the sense resistor

Due to the collector current density difference between the first bipolar transistor Qi and the second bipolar transistor Q ₂ , a base emitter voltage difference, δVbe, is developed across the sense resistor n resulting in a PTAT current which biases the second bipolar transistor Q ₂ . The PTAT current derived from the base emitter voltage difference, δVbe, may be varied by trimming the trimming element ri_ _trιm of the sense resistor n. The output of the amplifier A1

drives a current mirror arrangement comprising four PMOS transistors MPi, MP ₂ , MP ₃ , and MP ₄ for mirroring the PTAT current derived from the δVbe. The four PMOS transistors of the current mirror have the same aspect ratios "Width" and "Length" VWL and each having their gates coupled to the output of the amplifier Ai and their sources coupled to the power supply V _dc ι. As a result their drain currents are substantially equal to the PTAT current derived from the δV _be arising from the collector current density differences between the first and second bipolar transistors Qi and Q ₂ . The drain current of MP ₄ provides the first PTAT current l_PTATi, and the drain current of MP ₃ provides the second PTAT current I_PTAT ₂ . As the MOS devices are substantially equivalent to one another, each of the two PTAT currents are also substantially equal. Similarly, the drain current of MPi which biases the first bipolar transistor Qi is a PTAT current and is substantially equal to l_PTATi and I_PTAT ₂ .

The CTAT current generator comprises an operational amplifier A ₂ having an inverting input, non-inverting input and an output. The non-inverting input of the amplifier A ₂ is coupled to the emitter of the first bipolar transistor Qi so that a base emitter voltage V _be is applied to the non-inverting input of the amplifier A ₂ . A sense resistor r2 is coupled between the inverting input of the amplifier A ₂ and the ground node gnd. The output of the amplifier A ₂ drives the gate of an NMOS transistor MNi which has its source coupled to the sense resistor r ₂ and its drain coupled to the summation node which is also coupled to the drain of the PMOS transistor MP ₃ which provides the second PTAT current I_PTAT ₂ . The amplifier A ₂ forces the voltage on its inverting input to be equal to the voltage at its non-inverting input. Thus, the voltage at the inverting input Of A ₂ is equal to the base emitter voltage of Qi. Therefore a base emitter voltage V _be is dropped across r ₂ which results in a CTAT current I_CTAT flowing through r ₂ . The NMOS transistor MNi mirrors the CTAT current I_CTAT. As the second PTAT current l_PTAT ₂ is provided by a PMOS transistor, and the CTAT current I_CTAT is provided by an NMOS transistor I_CTAT is of opposite polarity to

I_PTAT ₂ . At the summation node which is common to the drains of MP3, MNI and the inverting input of the amplifier A I_CTAT subtracts from I_PTAT ₂

The operation of reference voltage circuit 300 is substantially similar to that of the reference voltage circuit 200. The first PTAT current l_PTATi flows through resistor r ₃ resulting in a PTAT, δV _be , voltage dropped across r ₃ . The CTAT current I_CTAT is a negative current, and the second PTAT current I_PTAT ₂ is a positive current. At room temperature I_CTAT and I_PTAT ₂ are generated to be of equal magnitude and opposite in polarity and as a result at the summation node I_CTAT subtracts from I_PTAT ₂ which results in zero current flowing through the feedback resistor r ₄ .

At room temperature the zero difference between I_PTAT ₂ and I_CTAT corresponds to:

WJM ₌ VJM _{or VbλTo) = AVbλTor} H ₍₉₎ r _x r ₂ r _γ

For a zero offset voltage amplifier the output voltage, which is the reference voltage, corresponds to the voltage applied at the non-inverting input of amplifier A minus the voltage drop across r4 due to the current difference between l_ PTAT ₂ and I_CTAT.

T r T r V — T * r - (J — J \ * r — KV (T \ * * -^- — \V (T \ * * -i-

¹ O ^r \ ¹ O ^r \

+ Ko * *- (10)

The reference voltage V _rβ f can be separated into three terms as given by equation 11 , namely, a temperature independent term, a linear temperature dependent term, and a curvature term.

In order to get a temperature insensitive voltage from equation 11 a second condition needs to be set which is given by equation 12.

At a second predetermined temperature, preferably higher than the first predetermined temperature, the feedback resistor r ₄ is set such that the reference voltage remains as it was at the first temperature T ₀ . ( V^-^) ' (i2)

Thus:

AV _be (T ₀ ) * í = V * ^ or r _o = δK _te (7i) * _L * _l (13) r _x r ₂ r _x r ₄

Now incorporating equations 9 and 13 into equation 11 results in:

It will be appreciated that, the voltage curvature term V _cur v of the reference voltage circuit 300 has the same form as the voltage reference as in the prior art circuit 100. This second order curvature effect can be compensated for using suitable circuitry. As equation 14 shows the voltage reference at the output of the amplifier A is related to the base-emitter voltage difference δVbe at room temperature and a resistor ratio. Both terms can be set with high accuracy and they have very little process dependence. Advantageously, the voltage reference can be scaled to any value by scaling the resistor ratio r ₃ /ri.

It will be recalled that the teaching of the present invention provides for, at a first temperature, for the values of the CTAT and first PTAT element to substantially cancel each other. In the arrangement of Figure 3, a trimming resistor, r2_trim, is provided to allow for an adjustment of the CTAT current I_CTAT such that at room temperature, T ₀ , the injected current into the feedback resistor r ₄ is zero.

In this way, the first condition corresponding to zero feedback current, according to equation 9 is set by trimming r2_trim.

The second condition, corresponding to providing the temperature insensitivity according to equation 12 may be effected by trimming the resistance in the feedback path of the amplifier A by trimming r4_thm.

The trimming procedure for the reference voltage circuit 300 may be provided as follows. At a first temperature typically room temperature,T ₀ , variable resistor r1_trim (which can be provided in one of a number of different forms such as a string DAC) is adjusted such that the voltage measured at the inverting input of the amplifier A has the desired value. At the same temperature, T ₀ , r2_trim is adjusted such that the measured voltages at the inverting input and at the output of the amplifier A are the same. At a second temperature, Ti, which is desirably higher than the first temperature T ₀ , r4_trim is adjusted so that the reference voltage at the output of the amplifier A remains as it was at the first temperature T ₀ .

Referring now to the graph of Figure 4 which shows exemplary performance of the reference voltage of reference voltage circuit 300 plotted against temperature for the industrial temperature range (-40 ⁰ C to 85°C). l_PTATi, I_PTAT ₂ and I_CTAT were set to about 2μA at room temperature of 25°C. As the graph illustrates the reference voltage is about 1.25V with a bow of about 2.7mV which corresponds to a temperature coefficient, TC, of 17ppm/°C, using "box method", very similar to a voltage reference based on the bandgap principle. As was mentioned above, different solutions can be used to correct for the curvature error shown in the graph of Figure 4.

Referring now to Figure 5 a reference voltage circuit 400 is provided which is substantially similar to the reference voltage circuit 300 with the same components referenced by the same reference labels. The reference voltage

circuit 400 incorporates the reference voltage circuit 300 indicated by reference numeral 1 and a curvature compensation circuit indicated by reference numeral 2 which compensates for the curvature error.

The purpose of the curvature compensation circuit 2 is to force a current with exponential temperature dependence into the emitter of the bipolar transistor Qi the base emitter voltage of which is used to generate the CTAT current I_CTAT and to add a similar smaller current into the emitter of the high current density bipolar transistor Q ₂ from the PTAT current generator. A PTAT current is mirrored via a PMOS transistor MP5 and an NMOS transistor MN2. A fraction of the mirrored PTAT current is pulled via the NMOS transistor MN3 from the base terminal of a bipolar transistor Q ₃ . The emitter current of Q ₃ results in an exponential temperature dependent current which is mirrored via a PMOS transistor MP5 into the emitter of Qi and via the PMOS transistor MP8 into the emitter of a bipolar transistor Q ₄ . The base-emitter voltage of Q ₄ is then used to generate the CTAT current.

Referring now to Figure 6 which shows exemplary performance of the reference voltage of reference voltage circuit 400 plotted against temperature for the industrial temperature range (-40 ⁰ C to 85°C). l_PTATi, l_PTAT ₂ and I_CTAT were set to about 2μA at room temperature of 25°C. The residual curvature is 56μV which corresponds to a TC of 0.35 ppm/°C or about fifty times improvement compared to the uncorrected reference voltage circuit 300.

It will be understood that what has been described herein are exemplary embodiments of circuits which have many advantages over reference voltage circuit known heretofore. The main advantage of the exemplary embodiments is that the reference voltage is based on a very predictable voltage, namely, a base-emitter voltage difference. A further advantage is that the reference voltage has much less dependency on process variations compared to bandgap based voltage reference. Another advantage is that the reference voltage can

be scaled to any voltage value via a resistor ratio. A further advantage is that the reference voltage may be trimmed easy and with high accuracy.

While the present invention has been described with reference to exemplary arrangements and circuits it will be understood that it is not intended to limit the teaching of the present invention to such arrangements as modifications can be made without departing from the spirit and scope of the present invention. In this way it will be understood that the invention is to be limited only insofar as is deemed necessary in the light of the appended claims.

It will be understood that the use of the term "coupled" is intended to mean that the two devices are configured to be in electric communication with one another. This may be achieved by a direct link between the two devices or may be via one or more intermediary electrical devices.

Similarly the words comprises/comprising when used in the specification are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more additional features, integers, steps, components or groups thereof.