SCHEDULING METHOD, AND MULTI-CORE PROCESSOR SYSTEM

Title:

SCHEDULING METHOD, AND MULTI-CORE PROCESSOR SYSTEM

Document Type and Number:

WIPO Patent Application WO/2012/093488

Kind Code:

A1

Abstract:

Provided is a scheduling method whereby load is distributed among a plurality of processor cores without a single-core executable object being changed. A CPU (#0) detects, with a detection unit (303), that a child thread (302), which is generated from a parent thread (301) that is assigned to a CPU (#2), is assigned to a CPU (#1). After the detection, the CPU (#0) assesses whether the parent thread (301) and the child thread (302) are in mutually exclusive operations. If the parent thread (301) and the child thread (302) are in mutually exclusive operations, the CPU (#0) copies copy source data which is stored in a parent thread context region (311) to a copy destination parent thread context region (312). After the copying, the CPU (#0) computes a copy destination data address offset value on the basis of the address of the copy destination data and a prescribed value. After the computation, the CPU (#0) notifies the CPU (#1), by a notification unit (307), of the copy destination data address offset value.

Inventors:

YAMASHITA KOICHIRO (JP)
YAMAUCHI HIROMASA (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)

Application Number:

PCT/JP2011/050187

Publication Date:

July 12, 2012

Filing Date:

January 07, 2011

Export Citation:

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Assignee:

FUJITSU LTD (JP)
YAMASHITA KOICHIRO (JP)
YAMAUCHI HIROMASA (JP)
SUZUKI TAKAHISA (JP)
KURIHARA KOJI (JP)

International Classes:

G06F9/50; G06F9/48; G06F12/0815

Foreign References:

JPH10143382A	1998-05-29
JP2000242510A	2000-09-08
JPH10198644A	1998-07-31
JP2007504535A	2007-03-01
JP2003029984A	2003-01-31
JPH05127904A	1993-05-25
JPH09146904A	1997-06-06

Other References: