Field of the Invention

This invention relates to the manufacture of semiconductor circuit devices. More specifically the invention relates to manufacture of multilayer semiconductor circuit devices in which isolation of levels of polysilicon is achieved.

Background of the Invention

The invention uses various materials which are electrically either conductive, insulative or semiconductive, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the semiconductor materials used is silicon, which appears as single crystal silicon and polycrystalline silicon material, referred to as "poly" throughout this disclosure.

Sidewall isolation of all polysilicon layers is necessary in the construction of high density high performance semiconductor circuit devices utilizing salicide process techniques. One prior art process is to form a sidewall oxide spacer using an oxide deposition and anisotropic etchback technique. Other approaches oxidize the poly 2, leaving the top and sidewall of the second level poly ("poly 2") to be capped off with oxide. Sheet resistance would then be high for poly 2. The several steps required by spacer oxide formation can result in poly 2 to active region

shorts under certain conditions.

Titanium suicide local interconnects have been extensively used to make contact to N+/P+ active area and to act as local routings connecting gates and N+/P+ active area in VLSI circuits. In one process, silicon is sputtered onto a surface which has been coated with a thin titanium blanket, and a local interconnect mask is used to define the interconnection pattern in the polysilicon. This approach requires a special etch that has high selectivity to the underlying refractory metal and it is often difficult to obtain good uniformity in the thin polysilicon layer prepared by the sputtering technique. In another system, TiN (one of the by-products in the silicidation process) is used as the local interconnect material, even though the resistivity of TiN is much higher than iSi2. Other techniques have been applied in order to establish electrical connection to trench structures, in which silicon is reacted with a refractory metal in order to form a conductive suicide strap across a trench.

Conventional processes for establishing interconnects on dynamic random access memory semiconductor devices (DRAMs) have included the use of metallization layers (eg., aluminum), which form bitlines and other local interconnects via a non self-aligned contact scheme, limiting the minimal spacing allowed between the access transistors. The proposed iSi2 interconnect provides a low resistance self-aligned contact procedure for the bitline formation, and greatly reduces the spacing necessary between the access

transistors, thus enabling a more efficient/compact layout of the memory cell.

Suicide coatings increase the speed and efficiency of DRAMs and similar semiconductors by reducing sheet resistance of silicon circuit elements, and consequently reducing the RC delay of circuits including these elements. This can be seen by examining typical sheet resistances, given in ohms per square, although the specific circuit configuration would determine the exact sheet resistances. Polysilicon has a typical sheet resistance of approximately 20Ω/square. N+ material typically exhibits a sheet resistance of 35Ω/square, and P+ material typically exhibits a sheet resistance of 60Ω/square. TiSi2 typically has a sheet resistance of less than 1 Ω/square, so that silicon material coated with the TiSi2 would also have a sheet resistance of less than 1 Ω/square.

This invention relates to the salicidation of conductive levels on DRAM semiconductor devices. In the salicide process, silicidation is performed after transistor gates are defined, so that the suicide interconnects are self aligned. This proceedure also permits the transistor source and drains to be established prior to the sputtering of refractory metal. Under the prior art process limitations, a double level poly salicide process would require capping off the second level poly with oxide; thus not allowing that level to be salicide strapped. It is therefore desired to provide a salicide process in which the second level of poly may be strapped.

While these needs initially are being addressed for 1Meg and 4Meg DRAMs, it is anticipated that the inventive techniques will be used for higher and lower capacity DRAMs.

It is also anticipated that these needs would be used for other very large scale integrated circuit (VLSI) semiconductor devices.

Summary of the Invention

This invention relates to the salicidation of conductive levels on DRAM semiconductor devices. It provides for a consistant and efficient sidewall isolation of a later level of polysilicon thus allowing this level to be strapped with salicide as well as previous poly levels and active areas. The salicidation of all conductive levels reduces sheet resistance and improves speed.

In accordance with the present invention, a first nitride level is deposited, over a first poly layer, for use as cell dielectric. A second poly layer is deposited over the nitride level, followed by a second level of nitride. The second poly layer and the second lever of nitride are patterned with a photoresist material and etched, by first etching the nitride then etching the poly. The resist is then removed and the surface is exposed to thermal oxidation. Finally, the nitride on top of poly 2 and the original nitride exposed after the poly 2 etch are removed simultaneously in a selective etch.

The surface of active areas, including both poly layers, are now free to be exposed to a selective salicide formation process.

In the salicide formation process, a poly pattern is established, along . with source and drain implants. Oxide is established along poly sidewalls in a manner which permits sidewall isolation. A refractory metal, such as titanium is sputtered onto the top surface of the wafer and is sintered in a nitrogen atmosphere. TiSi2 is formed where the titanium is exposed to elemental silicon, while oxide patterns result in the titanium reacting only with the nitrogen. The titanium nitride and any unreacted titanium may then be selectively etched, leaving a desired pattern of TiSi2«

The invention makes use of a nitride-poly-nitride stack to isolate a region of the poly which is subsequently oxidized. Nitride at the bottom of the sandwich protects all other regions from this oxidation step. Nitride on top protects the poly upper surface from the same oxidation, so that only the sidewall of the poly is oxidized.

The nitride barrier on the upper surface of the later level poly inhibits oxidation and allows this poly to be strapped with salicide while the sidewall oxide protects against shorts by inhibiting salicidation at the sidewall.

The invention allows for the salicidation of a second level of poly in addition to the previous poly level and the active area, and provides the

advantage of an improved sidewall isolation over prior art CVD oxide spacers.

The nitride-poly-nitride stack offers several advantages over previous process methods:

1 ) The oxide sidewall produced by this process is of uniform thickness and does not thin out at the bottom as an oxide spacer could. This process avoids problems seen with oxide spacers associated with the poly 2 sidewall profile, in which low angle profiles were not fully covered after spacer formation.

2) Spacer formation for poly ^" 2 would result in a "double spacer" for poly 1 that unduely increases the series resistance from the salicided source/drain to the transistor channel region. This compromises some of the potential performance improvement provided by salicidation.

3) Eliminating the second spacer deposition and etch avoids detrimental field isolation oxide thinning (spacer 2 overetch) that can compromise high voltage operation and performance. Also during overetch, recession of the isolation LOCOS edge may occur. This LOCOS recession can lead to salicide spiking through the diffusion junction due to the effective junction depth reduction at the junction/LOCOS sidewall. In practice, the second spacer over- etch acts to limit the minimum available diffusion junction depth. This restricts scaling of the transistor devices.

4) Eliminating the second spacer etch avoids problems associated with source/drain diffusion silicon etching during the spacer overetch. This silicon etch results from finite selectivity of the anisotropic dry etch used during spacer formation.

5) This process allows for selective "non-salicidation" , in that it is possible to selectively avoid salicidation of poly 1 without adding process steps. This is done by simply overlapping poly 2 over poly 1. All poly 1 overlapped by poly 2 will not be subject to the salicide or suicide process.

6 ) Relatively easy steps are required to facilitate salicidation (silicidation) of poly 2; that is extra nitride deposition and etch, and extra steam oxidation. This contrasts with the difficult steps associated with spacer formation. Spacer oxide formation requires more steps than this nitride-poly-nitride process and can result in poly 2-to-active region shorts under certain conditions.

Brief Description of the Drawings

Figure 1 shows a cross-sectional view of a poly 1 and poly 2, indicating the nitride-poly-nitride stack;

Figure 2 shows the wafer of Figure 1 after poly 2 pattern and etch;

Figure 3 shows resist strip and the subsequent sidewall oxidation;

Figure 4 shows the resulting structure after nitride etch;

Figure 5 shows a blanket layer of titanium sputtered onto the surface of the wafer; and

Figure 6 shows the wafer after salicide.

Detailed Description of the Preferred Embodiment

After initial preparation, a wafer 13 is processed through a series of steps which result in a circuit pattern being formed on the wafer as a part of the wafer. The initial preparation is generally standard preparation used to prepare the wafer for the processing. After the initial processing, oxide , which includes gate oxide 15, is grown on the wafer 13, and the underlying portion of the wafer forms a substrate.

A first level of polysilicon, referred to as poly 1 , is applied and a layer of oxide is grown over the wafer 13. The oxide is later stripped, but source/drain reox 23 remains.

An oxide-spacer 25 is used to offset the poly 1 , which forms a transistor gate structure, from source and drain regions. The oxide-spacer helps to prevent shorting of the source/drain regions to the edge of the transistor gate during salicide formation.

A thin blanket layer of nitride 27 is deposited on top of the surface of the wafer 13. The nitride 27 is preferably deposited on the surface by chemical vapor deposition (CVD) , although the nitride 27 may be grown or deposited in any of a variety of manners. This nitride layer 27 forms cell dielectric and electrically isolates the second poly layer (poly 2) from the substrate N+ region. -

The Poly 2 deposition is followed by thermal phosphorus doping using PH3 gas. This is preferrably done at a temperature of approximately 900 degrees C with a range of temperature between 700 and 1100 degrees C. The second polysilicon layer (poly 2) deposition is followed by a second level of nitride 37.

The second level of nitride and poly 2 are patterned with a photoresist material 39 and etched, first etching the nitride then etching poly 2, as shown in Figure 2.

Referring to Figure 3, the resist 39 is then removed and the surface of the wafer 13 is exposed to thermal oxidation to form a sidewall oxide ^* layer 41. A short oxide etch follows to clear a thin oxide which is grown on the exposed surfaces, of the nitride layers 27, 37. This is followed by a nitride etch which clears the second nitride layer 37 from the surface of poly 2 and any exposed nitride 27 from the surface of the remaining circuitry, as shown in Figure 4.

The surface of the wafer 13 may now be exposed to a selective silicide formation process.

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A blanket layer of ~600A titanium is sputtered onto the surface of the wafer 13, as shown in Figure 5. A low temperature (~650C) sinter then is performed in N ambient. During the sintering step, titanium reacts with the silicon to form titanium silicide, primarily TiSi2. The titanium does not react with the oxide (Siθ2), but instead becomes TiN or remains as elemental titanium.

The location of the spacer oxide 25 and the sidewall oxide 41 coincide with locations where silicide formation is not desired, and where TiSi does not form. The TiN and unreacted titanium are washed from the wafer 13 in a salicide piranha, which is a wet etch which leaves the TiSi2 in place, as shown in Figure 6. After removing the unreacted Ti and TiN by a wet etch, a silicide anneal (~800C) is performed to lower the sheet resistivity of the TiSi2 layer.