Title:
SEMICONDUCTOR ARITHMETIC CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1996/030855
Kind Code:
A1
Abstract:
A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuits each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuits. The output signals of all the inverters in the inverter circuit group, the output signal of a logical operation circuit generated by passing the output signals of the inverters through a multistage inverter circuit and inputting them into the logical operation circuit, or the output signal of a multistage inverter circuit generated by passing the output signal of the logical operation circuit through the multistage inverter circuit is fed back to at least one second input gate of the inverter circuits in the inverter circuit group.
Inventors:
SHIBATA TADASHI (JP)
OHMI TADAHIRO (JP)
MORIMOTO TATSUO (JP)
KAIWARA RYU (JP)
OHMI TADAHIRO (JP)
MORIMOTO TATSUO (JP)
KAIWARA RYU (JP)
Application Number:
PCT/JP1996/000771
Publication Date:
October 03, 1996
Filing Date:
March 25, 1996
Export Citation:
Assignee:
SHIBATA TADASHI (JP)
OHMI TADAHIRO (JP)
MORIMOTO TATSUO (JP)
KAIWARA RYU (JP)
OHMI TADAHIRO (JP)
MORIMOTO TATSUO (JP)
KAIWARA RYU (JP)
International Classes:
G06N3/063; (IPC1-7): G06G7/60
Foreign References:
| JPH06244375A | 1994-09-02 | |||
| JPS55124895A | 1980-09-26 |
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