Title:
SEMICONDUCTOR ASSEMBLY AND OPERATION METHOD THEREFOR, AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/026979
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure is a semiconductor assembly. The semiconductor assembly comprises: a substrate; an active pillar array structure located on the substrate, the active pillar array structure comprising a plurality of active pillars arranged in an array in a second direction and a third direction, each active pillar extending in a first direction, the first direction being parallel to the plane of the substrate, the second direction being parallel to the plane of the substrate and perpendicular to the first direction, and the third direction being perpendicular to the plane of the substrate, wherein each active pillar comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are sequentially stacked in the second direction; and a plurality of first word lines and a plurality of second word lines, which extend in the third direction, wherein each active pillar arranged in the third direction corresponds to one first word line and one second word line, each first word line covers the first semiconductor layer of the active pillar corresponding thereto, and each second word line covers the third semiconductor layer of the active pillar corresponding thereto.
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Inventors:
LIU YOUMING (CN)
Application Number:
PCT/CN2022/118611
Publication Date:
February 08, 2024
Filing Date:
September 14, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/105
Foreign References:
| CN114141715A | 2022-03-04 | |||
| CN105097818A | 2015-11-25 | |||
| US20100001339A1 | 2010-01-07 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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