Title:
SEMICONDUCTOR CHIP INTEGRATED ELEMENT
Document Type and Number:
WIPO Patent Application WO/2017/025003
Kind Code:
A1
Abstract:
Provided is a semiconductor chip integrated element, comprising a first lead structure (310), a second lead structure (320), and N third lead structures (330) stacked between said two lead structures, a semiconductor chip being connected between the chip trays of each two adjacent lead structures, a plurality of semiconductor chips being integrally packaged to form a semiconductor chip integrated element; the lower surface of the chip tray (312) of the first lead structure (310) is provided with a first boss (313) matching and connected to an electrode of a semiconductor chip, the upper surface of the chip tray (322) of the second lead structure (320) is provided with a second bass (323) matching and connected to an electrode of a semiconductor chip, and the upper surface and the lower surface of the chip tray (332) of each third lead structure (330) are respectively provided with a third boss (333) matching and connected to an electrode of a semiconductor chip; packaging of the semiconductor chips of the various structures can be implemented, resolving the problem of misaligned connections and solder overflow when packaging semiconductor chips.
Inventors:
GOU YINGANG (CN)
WANG JIU (CN)
GAO GUILI (CN)
LI YONGYANG (CN)
WANG JIU (CN)
GAO GUILI (CN)
LI YONGYANG (CN)
Application Number:
PCT/CN2016/093884
Publication Date:
February 16, 2017
Filing Date:
August 08, 2016
Export Citation:
Assignee:
SHENZHEN BENCENT ELECTRONICS CO LTD (CN)
International Classes:
H01L23/498; H01L23/488; H01L23/49
Foreign References:
| CN105047641A | 2015-11-11 | |||
| CN103887292A | 2014-06-25 | |||
| CN103824853A | 2014-05-28 | |||
| US8952509B1 | 2015-02-10 |
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