SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND JIG FOR FORMING WIRING

WIPO Patent Application WO/2013/021847

A1

This semiconductor device manufacturing method has: a first step, wherein a pair of penetrating electrodes that penetrate a substrate in the thickness direction, and a pair of vertical electrodes connected to one surface of the substrate by being extended in the substrate in the thickness direction are formed, and common wiring that connects the pair of vertical electrodes to a device layer on the substrate is formed; a second step, wherein connecting wiring is formed, said connecting wiring connecting with each other one penetrating electrode out of the pair of penetrating electrodes, and one vertical electrode out of the pair of vertical electrodes; and a third step, wherein substrates respectively having the device layers formed thereon are laminated, and the penetrating electrodes of one substrate and the penetrating electrode having no connecting wiring connected thereto out of the pair of penetrating electrodes of the other substrate are connected to each other, said the other substrate being laminated to face the one substrate.

IWATSU HARUO (JP)
MATSUMOTO TOSHIYUKI (JP)

PCT/JP2012/069319

February 14, 2013

July 30, 2012

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TOKYO ELECTRON LTD (JP)
IWATSU HARUO (JP)
MATSUMOTO TOSHIYUKI (JP)

H01L27/10; H01L21/3205; H01L21/768; H01L23/522; H01L25/065; H01L25/07; H01L25/18; H01L27/00

JP2009010390A	2009-01-15
JP2008227447A	2008-09-25
JP2007250561A	2007-09-27
JP2006165073A	2006-06-22
JP2005122823A	2005-05-12

KANEMOTO, Tetsuo et al. (JP)
Tetsuo Kanamoto (JP)

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