Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM
Document Type and Number:
WIPO Patent Application WO/1999/016175
Kind Code:
A1
Abstract:
A semiconductor integrated circuit including a Galois multiplier which enables multiplication using a plurality of different primitive polynominals. The semiconductor integrated circuit (1) includes a Galois multiplier (2) which is used for Galois multiplication of the elements of a Galois field GF(2?n¿). The coefficients (5, 4) of the elements of the Galois field GF(2?n¿) which are the multiplier and the multiplicand and the coefficients (6) of the primitive polynominals are inputted to the Galois multiplier. The coefficients are arithmetically operated for different primitive polynominals with the same hardware to obtain Galois multiplication results. A coefficient setting means (3) which supplies the coefficients of the primitive polynominals of the Galois field GF(2?n¿) is provided. With this constitution, the Galois multiplier can perform multiplication on the Galois field corresponding to the primitive polynominals supplied by the coefficient setting means. The semiconductor integrated circuit, therefore, can be versatilely applied to encoding or decoding of the error correction codes of the different Galois fields which are defined for the different primitive polynominals respectively.
Inventors:
OZAWA TOSHIMITSU (JP)
KANEKO KENJI (JP)
KOJIMA HIROTSUGU (JP)
YAMAUCHI TSUKASA (JP)
KATAYAMA YUKARI (JP)
KANEKO KENJI (JP)
KOJIMA HIROTSUGU (JP)
YAMAUCHI TSUKASA (JP)
KATAYAMA YUKARI (JP)
Application Number:
PCT/JP1997/003367
Publication Date:
April 01, 1999
Filing Date:
September 24, 1997
Export Citation:
Assignee:
HITACHI LTD (JP)
OZAWA TOSHIMITSU (JP)
KANEKO KENJI (JP)
KOJIMA HIROTSUGU (JP)
YAMAUCHI TSUKASA (JP)
KATAYAMA YUKARI (JP)
OZAWA TOSHIMITSU (JP)
KANEKO KENJI (JP)
KOJIMA HIROTSUGU (JP)
YAMAUCHI TSUKASA (JP)
KATAYAMA YUKARI (JP)
International Classes:
G06F7/72; H03M13/15; H03M13/47; (IPC1-7): H03M13/00; G11B20/18
Foreign References:
| JPS6399623A | 1988-04-30 | |||
| JPS63221426A | 1988-09-14 | |||
| JPH04229725A | 1992-08-19 | |||
| JPH09115244A | 1997-05-02 | |||
| JPS63104526A | 1988-05-10 | |||
| JPH0286334A | 1990-03-27 | |||
| JPS62269426A | 1987-11-21 | |||
| JPH09167360A | 1997-06-24 | |||
| JPS63206967A | 1988-08-26 |
Other References:
C. PAAR, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields", IEEE TRANS. ON COMPUTERS, Vol. 45, No. 7, July 1996, pp. 856-861.
Attorney, Agent or Firm:
Tamamura, Shizuyo (Kosumo Matsudo Station Square 1333-1, Matsud, Matsudo-shi Chiba 271, JP)
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