Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/101226
Kind Code:
A1
Abstract:
According to the present invention, a capacitor cell includes an active region (2P) and a power supply wiring (11) that supplies VDD. The active region (2P) includes nanosheets (21b-21e) extending in the X direction as channels of transistors (P2-P5). The power supply wiring (11) extends in the X direction on the back side of the transistors (P2 to P5) and overlaps the active region (2P) in a plan view. The sources/drains of the transistors (P2 to P5) in the active region (2P) are connected to the power supply wiring (11) via vias (61). VSS is applied to the gate wirings (31b to 31e) of the transistors (P2 to P5).
Inventors:
HINO TOSHIO (JP)
Application Number:
PCT/JP2023/039287
Publication Date:
May 16, 2024
Filing Date:
October 31, 2023
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82; H01L21/822; H01L21/8234; H01L27/04; H01L27/06
Domestic Patent References:
| WO2021171969A1 | 2021-09-02 | |||
| WO2020066797A1 | 2020-04-02 |
Foreign References:
| US20220157804A1 | 2022-05-19 | |||
| US20210336001A1 | 2021-10-28 | |||
| US20210375853A1 | 2021-12-02 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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