Title:
SEMICONDUCTOR INTEGRATED CIRCUIT AND PULSE GENERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2014/030209
Kind Code:
A1
Abstract:
A semiconductor integrated circuit quickly determines a pulse width based on transistor characteristics and capable of writing a latch circuit, in such a way that: a plurality of pulses having different pulse widths are generated by a plurality of chopper circuits; a plurality of operation confirmation latch circuits latch a changed input value by using the respective pulses; and a chopper circuit with a pulse width variable function changes the pulse width of a pulse for driving the latch circuit on the basis of the outputs of the operation confirmation latch circuits and generates and outputs the pulse having the changed pulse width.
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| JP4676762 | Sample hold circuit |
Inventors:
HOSHIMOTO AKITAKA (JP)
TAKEDA HIDEO (JP)
TAKEDA HIDEO (JP)
Application Number:
PCT/JP2012/071060
Publication Date:
February 27, 2014
Filing Date:
August 21, 2012
Export Citation:
Assignee:
FUJITSU LTD (JP)
HOSHIMOTO AKITAKA (JP)
TAKEDA HIDEO (JP)
HOSHIMOTO AKITAKA (JP)
TAKEDA HIDEO (JP)
International Classes:
H03K5/00; H03K5/04
Foreign References:
| JPH03273413A | 1991-12-04 | |||
| JP2000196419A | 2000-07-14 |
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
Takayoshi Kokubu (JP)
Takayoshi Kokubu (JP)
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