Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1999/066640
Kind Code:
A1
Abstract:
A semiconductor integrated circuit which comprises a logic circuit block (8) synchronized in operation with a clock signal, power supply switches (12, 14) for supplying electric power to the logic circuit block, and a power supply switch control circuit (2) for controlling the power supply switches in such a way as to turn on the power supply switches for a time shorter than the period of the clock signal in synchronism therewith. Assuming that the logic circuit block is operated in synchronism with a clock signal having a frequency lower than that of the clock signal determining the maximum operating speed of the logic circuit block, erroneous operation does not take place theoretically if the logic circuit block is operated only for a time determined by the clock signal frequency of the maximum operating speed. Since operating power supply to the logic circuit block is interrupted except during the time required for the operation of the circuit, leak current tending to flow into an off-state transistor can be reduced significantly.
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Inventors:
HATAE HIROSHI (JP)
Application Number:
PCT/JP1998/002685
Publication Date:
December 23, 1999
Filing Date:
June 18, 1998
Export Citation:
Assignee:
HITACHI LTD (JP)
HATAE HIROSHI (JP)
HATAE HIROSHI (JP)
International Classes:
H03K19/00; (IPC1-7): H03K3/037; H03K19/096; H01L27/092
Foreign References:
| JPS607224A | 1985-01-16 | |||
| JPS59224915A | 1984-12-17 | |||
| JPS59224914A | 1984-12-17 | |||
| JPH0629834A | 1994-02-04 | |||
| JPH08321763A | 1996-12-03 | |||
| JPH05291929A | 1993-11-05 | |||
| JPH05108194A | 1993-04-30 | |||
| JPH06112810A | 1994-04-22 |
Attorney, Agent or Firm:
Tamamura, Shizuyo (Kosumo Matsudo Station Square 1333-1, Matsud, Matsudo-shi Chiba, JP)
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