Title:
SEMICONDUCTOR MEMORY DEVICE AND ADDRESS CONVERSION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2002/045093
Kind Code:
A1
Abstract:
A semiconductor memory device including a memory cell array requiring refresh such as a DRAM and a memory cell array not requiring refresh such as an SRAM which are usable by allocating external addresses to them comprises a redundant circuit suited to the structure. A semiconductor memory device comprises a DRAM cell array (11) of dynamic memory cells, an SRAM cell array (12) of static memory cells, a predecoder (101) for converting an external address Add to a raw predecode signal A1 or A2 corresponding to either the DRAM cell array (11) or the SRAM cell array (12), a redundancy program circuit (103) for specifying a memory cell of the DRAM cell array (11) the characteristic defect is to be remedied, and a redundancy judging circuit (102) for converting the external address Add of the specified memory cell to a raw predecode signal A4 to be sent to a predetermined memory cell in the SRAM cell array (12).
Inventors:
TAKAHASHI HIROYUKI (JP)
Application Number:
PCT/JP2001/010335
Publication Date:
June 06, 2002
Filing Date:
November 27, 2001
Export Citation:
Assignee:
NEC CORP (JP)
TAKAHASHI HIROYUKI (JP)
TAKAHASHI HIROYUKI (JP)
International Classes:
G11C8/02; G11C11/408; G11C29/00; (IPC1-7): G11C29/00; G11C11/401; G11C11/41
Foreign References:
| JPH10289595A | 1998-10-27 | |||
| JPS6459700A | 1989-03-07 | |||
| JP2000260197A | 2000-09-22 |
Attorney, Agent or Firm:
Hamada, Haruo (Minami-Aoyama 3-chome Minato-ku, Tokyo, JP)
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