Title:
SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS
Document Type and Number:
WIPO Patent Application WO/1997/032253
Kind Code:
A1
Abstract:
A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.
Inventors:
KATAYAMA KUNIHIRO (JP)
TAMURA TAKAYUKI (JP)
WATATANI SATOSHI (JP)
INOUE KIYOSHI (JP)
SHIOTA SHIGEMASA (JP)
NAITO MASASHI (JP)
TAMURA TAKAYUKI (JP)
WATATANI SATOSHI (JP)
INOUE KIYOSHI (JP)
SHIOTA SHIGEMASA (JP)
NAITO MASASHI (JP)
Application Number:
PCT/JP1996/003501
Publication Date:
September 04, 1997
Filing Date:
November 29, 1996
Export Citation:
Assignee:
HITACHI LTD (JP)
KATAYAMA KUNIHIRO (JP)
TAMURA TAKAYUKI (JP)
WATATANI SATOSHI (JP)
INOUE K (JP)
SHIOTA SHIGEMASA (JP)
NAITO MASASHI (JP)
KATAYAMA KUNIHIRO (JP)
TAMURA TAKAYUKI (JP)
WATATANI SATOSHI (JP)
INOUE K (JP)
SHIOTA SHIGEMASA (JP)
NAITO MASASHI (JP)
International Classes:
G11C7/00; G11C11/34; G11C16/06; G11C29/00; H04L12/28; G06F11/20; (IPC1-7): G06F12/16; G11C16/06; G11C29/00
Foreign References:
| JPH04311236A | 1992-11-04 | |||
| JPH04308971A | 1992-10-30 | |||
| JPH0567005A | 1993-03-19 | |||
| JPH05274219A | 1993-10-22 | |||
| JPH0620483A | 1994-01-28 | |||
| JPH0756816A | 1995-03-03 | |||
| JPH03131951A | 1991-06-05 | |||
| JPS62239252A | 1987-10-20 | |||
| JPS63219045A | 1988-09-12 |
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