Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/175730
Kind Code:
A1
Abstract:
A semiconductor memory device (1) comprises: a memory cell array (3) in which a plurality of memory cells (MC) are connected to a bit line pair (BLT); and a write circuit that sets a bit line on a low potential side to a negative potential in accordance with a negative potential burst signal. For a data read operation, when a first prescribed time has elapsed since an input clock signal transition, a word line is set to an active state so that a stored value at a memory cell is read. For a data write operation, when a second prescribed time which is longer than the first prescribed time has elapsed since the input clock signal transition, the word line is set to the active state, and when a third prescribed time which is longer than the first prescribed time has elapsed, the negative potential burst signal is set to an active state.
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Inventors:
MORIWAKI SHINICHI (JP)
Application Number:
PCT/JP2022/011673
Publication Date:
September 21, 2023
Filing Date:
March 15, 2022
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
G11C11/419; G11C11/418
Foreign References:
| JP2012069214A | 2012-04-05 | |||
| US20160118091A1 | 2016-04-28 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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