SEMICONDUCTOR STORAGE DEVICE AND SYSTEM PROVIDED WITH SAME

WIPO Patent Application WO/2014/142254

A1

[Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array (11) comprising a plurality of word lines including word lines (WLI, WL2) that are adjacent to one another; and a TRR address conversion unit (53) that selects the word line (WL1) in response to the input of an address signal (IADD) indicating a first value while in a first operation mode and selects the word line (WL2) in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.

JPS5674892	STORAGE CONTROLLING DEVICE
JP2011216168	MEMORY SYSTEM
JP2000113668	SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

NARUI SEIJI (JP)
NODA HIROMASA (JP)
DONO CHIAKI (JP)
NAKAMURA MASAYUKI (JP)
KONDO CHIKARA (JP)

PCT/JP2014/056720

September 18, 2014

March 13, 2014

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PS4 LUXCO SARL (LU)
NARUI SEIJI (JP)
NODA HIROMASA (JP)
DONO CHIAKI (JP)
NAKAMURA MASAYUKI (JP)
KONDO CHIKARA (JP)

G11C11/406

US20110122687A1	2011-05-26
JP2007184072A	2007-07-19
JP2011164669A	2011-08-25
JP2013004158A	2013-01-07
JP2013239228A	2013-11-28

WASHIZU Mitsuhiro et al. (JP)
Mitsuhiro Washizu (JP)

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