Title:
SEMICONDUCTOR SUBSTRATE EVALUATING METHOD AND SEMICONDUCTOR SUBSTRATE EVALUATING ELEMENT
Document Type and Number:
WIPO Patent Application WO/2008/072373
Kind Code:
A1
Abstract:
Provided is a semiconductor substrate evaluating method wherein at least the following
steps are performed. An isolating oxide film is formed on the surface of a semiconductor
substrate to open a window, and a gate oxide film is formed. On the gate oxide film
at the window section of the isolating oxide film, a gate electrode and two breakdown
electrodes on each side of the gate electrode are formed. In the semiconductor
to be evaluated between the electrodes, a dopant having a conductivity different
from that of the semiconductor is diffused, an electric field is applied between
the breakdown electrodes on the both sides of the gate electrode and the gate oxide
film is partially broken. Then, MOSFET measurement is performed by having the
breakdown electrodes adjacent to the both sides of the gate electrode as a source
electrode and a drain electrode, and the semiconductor substrate is evaluated.
Thus, the semiconductor substrate is easily evaluated by the evaluation method
employing the MOSFET structure without requiring a long time before finishing
evaluation and without using equipment and technologies for forming conventional
isolating oxide film for insulating metal wirings one from the other and for forming
conventional metal wiring.
Inventors:
OHTSUKI TSUYOSHI (JP)
Application Number:
PCT/JP2007/001378
Publication Date:
June 19, 2008
Filing Date:
December 10, 2007
Export Citation:
Assignee:
SHINETSU HANDOTAI KK (JP)
OHTSUKI TSUYOSHI (JP)
OHTSUKI TSUYOSHI (JP)
International Classes:
H01L21/66; H01L21/822; H01L27/04
Foreign References:
| JPH1022502A | 1998-01-23 | |||
| JP2005057153A | 2005-03-03 | |||
| JPH09205154A | 1997-08-05 |
Attorney, Agent or Firm:
YOSHIMIYA, Mikio (6-11 Ueno 7-chom, Taito-ku Tokyo 05, JP)
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