Title:
SPI NAND FLASH MEMORY DRIVEN BY PARALLEL PIPELINE DOUBLE LATCH
Document Type and Number:
WIPO Patent Application WO/2014/196753
Kind Code:
A1
Abstract:
The present invention relates to a SPI NAND flash memory comprising a parallel pipeline double latch. The SPI NAND flash memory comprises: a page buffer, a plurality of read latches and a plurality of write latches. When reading data, the SPI NAND flash memory simultaneously performs a step of reading data from the page buffer and storing the data in one read latch and a step of outputting data already stored in another read latch. Further, when recording data, the SPI NAND flash memory simultaneously performs a step of receiving data inputted from the outside and storing the data in one write latch and a step of recording data, which is already stored in another write latch, in a write register of the page buffer.
Inventors:
KIM YONG SOO (KR)
Application Number:
PCT/KR2014/004588
Publication Date:
December 11, 2014
Filing Date:
May 22, 2014
Export Citation:
Assignee:
INDUSTRIAL BANK KOREA (KR)
International Classes:
G11C16/06; G11C16/10; G11C16/26
Foreign References:
| KR20110110106A | 2011-10-06 | |||
| KR20090092776A | 2009-09-01 | |||
| KR20100087324A | 2010-08-04 | |||
| KR20030033679A | 2003-05-01 | |||
| KR20010109114A | 2001-12-08 | |||
| KR20100087328A | 2010-08-04 |
Attorney, Agent or Firm:
YANG, Ki Hyuk et al. (KR)
양기혁 (KR)
양기혁 (KR)
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