SQUARE ROOT CALCULATIONS ON AN ASSOCIATIVE PROCESSING UNIT

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from US provisional patent application 63/297,753, filed January 9, 2022, which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to calculations of square roots generally and to their digital calculation in particular.

BACKGROUND OF THE INVENTION

[0003] A square root of a number x, is a number y such that y ² = x, where the number x is known as the “radicand”. The number N of bits of the resultant square root y is half of the number of bits of radicand x. Thus, the square root of a 32-bit number is a 16-bit number.

[0004] For example, 15 = 3.8729..., which, in binary is:

3.8729 = 0011.1101111101111011

[0005] The square root function, written as “sqrt” in most computer languages, provides the closest integer to the number (thus, sqrt(15) = 3). For higher accuracy, the number may be multiplied by any even power of two and the result may be divided by 2 ^j . Thus, in this example, 2j may be 8, so 15 may be multiplied by 2 ⁸ = 256, which provides sqrt(15*256) = sqrt(3840) = 61.9677, which is about 61. In binary, 61 is 11 1101. Dividing this by 2 ^j = 2 ⁴ = 16, produces sqrt(15) = 61/16 = 11.1101.

[0006] Reference is now made to Fig. 1, which illustrates a prior art guessing and testing procedure for finding binary square roots of a variable X. The process iterates over bits of a proposed result, initialized to zero, and starts at the MSB (most significant bit) of X. Thus, in step 10, the variable CurrentResult is initially set to zero and the index n, indicating the location of the current bit being determined, is set to the number N-l, one less than the number of bits expected in the result.

[0007] In step 11, the method guesses that the value of the current bit in the square root is 1 and generates a guess using the value of the current bit along with any other bits for which a result has already been determined and stored in their locations within variable CurrentResult.

[0008] Since each bit of a binary number represents a power of 2 in a regular number (i.e., the ith bit represents 2 ¹ ), in step 11, the method adds 2 ¹ to the variable CurrentResult, which stores the previous result, to generate a variable Guess. Step 11 then computes the square value of variable Guess, according to the calculation described hereinbelow, and stores the result as a variable GuessSquared.

[0009] If the radicand X is greater than the computed square GuessSquared, as checked in step 14, the value of ith bit of variable CurrentResult is set to 1; otherwise, the value of the ith bit of variable CurrentResult is set to 0. In step 18, index i is reduced by one and the next bit is checked until no bits remain, as checked by step 19.

[0010] At each step, the square root becomes more accurate and after the last iteration (i.e., when the index i is at 0), the proposed result is the square root Y of radicand X.

[0011] Determining the square, in step 11, utilizes the fact that each new value is a sum of the result computed so far plus the value of the new bit guessed to equal 1. The square may therefore be computed using the algebraic identity:

(a + b) ² = a ² + 2ab + b ² (1) where the variable ‘a’ is variable CurrentResult and the variable ‘b’ is the value of the new bit

(i.e., 2 ¹ ). [0012] However, a ² was the value of variable GuessSquared in the last iteration and thus, the calculation per iteration is first of 2ab + b ² which is then added to the not-yet-updated value of variable GuessSquared to generate the current value of variable GuessSquared.

[0013] To simplify the calculations, step 14 can be calculated as “X - GuessSquared” and then the check is whether or not the result is positive or negative.

[0014] Unfortunately, even when using the value of variable GuessSquared from the last iteration, the method still has to multiply 2ab, which is more complicated with more bits.

SUMMARY OF THE PRESENT INVENTION

[0015] There is therefore provided, in accordance with a preferred embodiment of the present invention, a method for calculating a square root B having N bits of a number X having 2N bits. The method includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteration, the method includes locating a 1 at the squared location of bit bi in a CHECK variable, determining the value of bit bi from the result of a comparison of number X with a function of all previously found bits and a previous comparison outcome, shifting all previously found bits right 1 location in a CHECK variable, and adding the determined value of bit bi into its squared location in the CHECK variable.

[0016] Moreover, in accordance with a preferred embodiment of the present invention, the CHECK variable is of length 2N and, the determining uses only the relevant portion of the CHECK variable.

[0017] Further, in accordance with a preferred embodiment of the present invention, in the locating, the squared location is two bits to the right of the current locations of all previously found bits in the CHECK variable.

[0018] Still further, in accordance with a preferred embodiment of the present invention, the adding is implemented as an OR operation.

[0019] Moreover, in accordance with a preferred embodiment of the present invention, the method is implemented on an associative memory device or on a CPU.

[0020] There is also provided, in accordance with a preferred embodiment of the present invention, a square root calculator for calculating a square root B having N bits of a number X having 2N bits. The calculator includes a central processing unit (CPU) and a memory array having a plurality of memory cells organized into rows and columns. The memory array has one row for a CHECK variable and a second row for a PREY variable, the PREY variable being aligned with the CHECK variable. The CPU iterates on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteration, the CPU locates a 1 at the squared location of bit bi in the CHECK variable, determines the value of bit bi from the result of a comparison of number X with a function of all previously found bits and a previous comparison outcome, shifts all previously found bits right 1 location in the CHECK variable, and adds the determined value of bit bi into its squared location in the CHECK variable. [0021] Further, in accordance with a preferred embodiment of the present invention, the CHECK variable is of length 2N and the CPU uses only the relevant portion of the CHECK variable.

[0022] Still further, in accordance with a preferred embodiment of the present invention, the squared location is two bits to the right of the current locations of all previously found bits in the CHECK variable.

[0023] There is also provided, in accordance with a preferred embodiment of the present invention, a square root calculator for calculating a square root B having N bits of a number X having 2N bits. The calculator includes an associative processing unit (APU) and the APU includes a memory array, a multiple row decoder and a controller. The memory array has a plurality of memory cells organized into rows and columns, where one row stores a CHECK variable and a second row stores a PREV variable, the PREV variable being aligned with the CHECK variable. The multiple row decoder activates multiple rows at a time and the controller activates the multiple row decoder to iterate on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteration, the controller instructs the following operations: writing a 1 at the squared location of bit bi in the CHECK variable, determining the value of bit bi from the result of a comparison of number X with a function of all previously found bits and a previous comparison outcome, shifting all previously found bits right 1 location in the CHECK variable, and OR’ing the determined value of bit bi in its squared location with the CHECK variable.

[0024] Further, in accordance with a preferred embodiment of the present invention, the CHECK variable is of length 2N and, wherein the OR’ing uses only the relevant portion of the CHECK variable.

[0025] Finally, in accordance with a preferred embodiment of the present invention, the squared location is two bits to the right of the current locations of all previously found bits in the

CHECK variable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:

[0027] Fig. 1 is a flow chart illustration of a prior art guessing and testing procedure for finding binary square roots of a variable X;

[0028] Fig. 2 is a schematic illustration of a square root calculator to find square root B of variable X, constructed and operative in accordance with a preferred embodiment of the present invention;

[0029] Figs. 3, 4, 5 and 6 are schematic illustrations showing the operation of the calculator of Fig. 2 when determining the 15 ^th bit bis, the 14 ^th bit bu, the 13 ^th bit bi3, and an i ¹¹¹ bit bi of square root B, respectively;

[0030] Fig. 7 is a flow chart illustration of a method for most iterations as illustrated in Fig. 6;

[0031] Fig. 8 is a flow chart illustration of an alternative method for calculating square roots;

[0032] Fig. 9 is a tabular illustration of the values of the bits of a variable CHECK at the end of iterations 15 - 0; and

[0033] Fig. 10 is a schematic illustration of a portion of an associative processing unit for implementing a square root calculator, constructed and operative in accordance with a preferred embodiment of the present invention.

[0034] It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0035] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

[0036] Applicant has realized that there is no need to consider the value of the entire guessed value, as the prior art does. Instead, Applicant has realized that very few powers of 2 are involved in the initial iterations and that this fact can be exploited to simplify the calculations to bit operations, such as shift and OR. As a result, the complexity of the square root computation for an N-bit result is reduced from O(N ² ) to O(N).

[0037] Applicant has also realized that the result of the current test calculation can be used in the next iteration when the resultant value of the current bit is 1 while the result of the previous current test calculation can be used when the resultant value of the current bit is 0.

[0038] Take for example, a 32-bit number X whose square root value B is a 16-bit number.

Square root B can be represented in the following manner: bi5bi4bi3bi2bnbiobo9bo8bo7bo6bo5bo4bo3bo2boiboo

This can be written mathematically as:

B =Sj ⁵ _£ 2 ^£ (2) where the bit bi is 0 or 1.

[0039] Reference is now made to Fig. 2, which illustrates a square root calculator comprising a central processing unit (CPU) 10 and a memory array 12. Memory array 12 may comprise a multiplicity of rows 20, two of which are shown in Fig. 2. Each row 20 has a plurality of memory cells 22 within which one bit of data is stored. Memory cells 22 are also organized in columns 24 such that each memory cell 22 can be accessed by activating its row 20 and its column 24.

[0040] A 32-bit number (also called a “vector”) is stored in 32 separate memory cells 22 of one of rows 20. While the memory cells 22 may not be adjacent, typically, a 32-bit number is stored in order, with the most significant bit (MSB) stored in the leftmost location of the set of memory cells 22 and the least significant bit (LSB) stored in the rightmost location. Since bit locations are numbered from 0 to 31, the MSB is stored in bit location 31 and the LSB is stored in bit location 0.

[0041] Fig. 3, to which reference is now made, shows the operation of the present invention when determining the 15 ^th bit bis of square root B. Fig. 3 shows two variables PREV and CHECK stored in two rows 20a and 20b, respectively. In this example, variables PREV and CHECK may be stored in rows 20 with their bit locations aligned. Thus, bit location 30 of variable PREV is in the same column 24 as bit location 30 of variable CHECK.

[0042] For the 15 ^th bit bis, variable PREV may store 32-bit number X whose square root is to be found and variable CHECK may initially be set to all 0’s.

[0043] To find the value of the 15 ^th bit bis, the check is simply to determine if the difference between the 32-bit number X and the square of 15 ^th bit bis is positive when bis is set temporarily to 1. Mathematically this is written as:

X - (bis2 ¹⁵ ) ² >= 0 when bis is 1 (3)

[0044] However, in accordance with the present invention, since bis has been set to 1 and the square of 2 ¹⁵ is 2 ³⁰ , equation 3 can be rewritten as:

X - [(1*2 ³⁰ ] >= 0 (4) [0045] In accordance with a preferred embodiment of the present invention, to subtract 1*2 ³⁰ from X, CPU 10 may write a 1 in bit location 30 (which is the “squared location” of bit 15) of row 20b storing variable CHECK.

[0046] CPU 10 may then subtract the variable CHECK from the variable PREV to generate a TEST variable:

TEST = PREV - CHECK (5)

[0047] CPU 10 may then check if TEST is positive. If so, it may set bis to 1 and, in accordance with the present invention, may set bit 30 of CHECK to 1 (leaving the remaining bits at their initialized values of 0) and may update variable PREV in row 20a to the value of variable TEST. [0048] Otherwise, CPU 10 may set bis to 0, may change bit 30 of variable CHECK back to 0, and may make no change to variable PREV since there was no change to bit 30.

[0049] CPU 10 may now operate to determine the value of the 14 ^th bit, bu. To do so, it has to check if the difference between the 32-bit number X and the square of the sum of the 15 ^th bit bis (found previously) with the 14 ^th bit bu is positive when bu is set temporarily to 1. Mathematically, this is written as:

X - (bi ₅ 2 ¹⁵ + b _i4 2 ¹⁴ ) ² >= 0 (6)

[0050] Using the identity (a+b)(a+b) = a ² +2ab+b ² and setting 14 ^th bit bi4 temporarily to 1, we get:

[0051] Recall that the square of 2 ¹⁵ is 2 ³⁰ and that variable PREV stores the variable TEST from the previous iteration which equaled X - bis2 ³⁰ . Similarly, the square of 2 ¹⁴ is 2 ²⁸ . Also note that the 2ab term, 2(bis2 ¹⁵ ) * (1*2 ¹⁴ ), is equivalent to (bis2 ¹⁵ ) * (1*2 ¹⁵ ). Thus, equation 7 may be rewritten as: Which, when consolidated, becomes:

PREV- [(bi ₅ 2 ³⁰ + (1*2 ²⁸ )] >= 0 (9)

[0052] In accordance with a preferred embodiment of the present invention, to implement equation 6, CPU 10 may write a 1 in bit location 28 (which is the squared location of bit 14) of row 20b storing variable CHECK. Note that, as shown in Fig. 4 to which reference is now made, CHECK already has the value of bis in location 30 from the previous iteration.

[0053] The next steps may be similar to the previous iteration. CPU 10 may implement equation 5 (i.e., subtract variable CHECK from variable PREV to generate variable TEST).

[0054] CPU 10 may then check if variable TEST is positive. If so, it may set bu to 1 and may update variable PREV in row 20a to the value of variable TEST. Otherwise, CPU 10 may set bit bu to 0, and may make no change to variable PREV since there was no change to bit 28.

[0055] In accordance with a preferred embodiment of the present invention and in preparation for the next iteration described in more detail hereinbelow, in order to update variable CHECK, CPU 10 may first set location 28 back to 0, may shift variable CHECK right one bit, which may move bit bis to location 29 (as shown in Fig. 5 to which reference is now made), after which CPU 10 may add the determined value for bit bi4 to location 28 (also shown in Fig. 5).

[0056] CPU 10 may now operate to determine the value of the 13 ^th bit, bi3. To do so, it has to check if the difference between the 32-bit number X and the square of the sum of the 15 ^th bit bis, the 14 ^th bit bi4, and the 13 ^th bit bi3, is positive when bi3 is set temporarily to 1. Mathematically, this is written as:

X - (bi ₅ 2 ¹⁵ + bi ₄ 2 ¹⁴ +bi ₃ 2 ¹³ ) ² >= 0 (10)

[0057] Equation 10 is more complex; however, Applicant has realized that variables PREV and CHECK from the previous iteration store useful information. [0058] Using the identity (a+b)(a+b) = a ² +2ab+b ² , defining ‘a’ as the previous result (i.e., bis2 ¹⁵ + bi42 ¹⁴ ), and setting 13 ^th bit bi3 temporarily to 1, we get:

[0059] Recall that that variable PREV stores the variable TEST from the previous iteration which equaled X - (bis2 ¹⁵ + bi ₄ 2 ¹⁴ ) ² , and that the square of 2 ¹³ is 2 ²⁶ . Also note that the 2ab term, 2(bis2 ¹⁵ + bi ₄ 2 ¹⁴ )*(l*2 ¹³ ), is equivalent to (bis2 ¹⁵ + bi ₄ 2 ¹⁴ ) * (1*2 ¹⁴ ). Thus, equation 11 may be rewritten as:

PREV - [(b ₁₅ 2 ²⁹ + b _i4 2 ²⁸ ) + (1*2 ²⁶ )] >= 0 (12)

[0060] The second term in Equation 12 will become the updated version of variable CHECK. However, note that its bit locations are as follows: bis in bit location 29 (to where it was shifted in the last iteration, in preparation for equation 12), bi ₄ in bit location 28 (where it was placed at the end of the last iteration) and a 1 temporarily in bit location 26 (i.e. the squared location of bis). Applicant has realized that this is the value of variable CHECK after the previous iteration, OR’d with a 1 in bit 13’ s squared location.

[0061] The next steps may be similar to the previous iteration. CPU 10 may implement equation 5 (i.e., subtract variable CHECK from variable PREV to generate variable TEST).

[0062] CPU 10 may then check if variable TEST is positive. If so, it may set bit bis to 1 and may update variable PREV in row 20a to the value of variable TEST. Otherwise, CPU 10 may set bit bi3 to 0, and may make no change to variable PREV since there was no change to bit 26.

[0063] As in the previous iteration, in order to update variable CHECK, CPU 10 may first set location 26 back to 0, may shift variable CHECK right one bit, which may move bit bis to location 28 and bit bi ₄ to location 27 , after which CPU 10 may add the determined value for bit bi3 to location 26. [0064] It will be appreciated that, each iteration i to determine bit bi has to calculate the following:

PREV - [(... b _i+2 2 ²ⁱ⁺³ + bi+i2 ²ⁱ⁺² ) + (l*2 ²ⁱ )] >= 0 (13) where variable PREV exists from the previous iteration and the second term in Equation 13 is built from the previous version of variable CHECK. As shown in Fig. 6 to which reference is now briefly made, the bit locations are as follows: a 1 temporarily in bit location 2i (i.e., the squared location of bit bi), and the previously solved bits in order to its left, starting at bit location i+2 (i.e., two locations to its left).

[0065] In other words, the updated version of variable CHECK is the final version of variable CHECK from the previous iteration OR’d with a 1 in the squared location of bit bi.

[0066] The method for most iterations is shown in Fig. 7 to which reference is now made. In step 32, CPU 10 may OR variable CHECK from the previous iteration with a 1 in its 2i location (i.e., the squared location of bit bi). CPU 10 may then subtract (step 33) variable CHECK from variable PREV to generate variable TEST. CPU 10 may then check (step 34) if variable TEST is positive. If so, it may set (step 36) bit bi to 1 and may update (step 38) variable PREV in row 20a to the value of variable TEST. Otherwise, CPU 10 may set (step 40) bit bi to 0, and may make no change to variable PREV since there was no change to bit bi. To update variable CHECK, CPU 10 may first set (step 42) location 2i back to 0, may shift (step 44) variable CHECK right one bit, and then may add (step 46) the determined value for bit bi to location 2i of variable CHECK. Note that step 46 is only necessary if bit bi is 1, since location 2i was previously set back to 0. In step 48, index i is reduced by 1 and the process is repeated until index i is 0. For the 0 ^th iteration, the squared location for bit bo is the 0 ^th bit location.

[0067] It will be appreciated that, when the process finishes, variable CHECK has shifted totally to the right and the 16 bits bi of square root B have been determined. [0068] It will be appreciated that the, as mentioned hereinabove, the addition operation can be replaced with an OR operation since the operands PREV and CHECK are disjoint since there are 2 bits between bi in its squared location (2 ²¹ ), and the previously solved bits (from 2 ²¹⁺² on). In other words, the new bits in each iteration do not overlap old bits from previous iterations and therefore, there will never be a carry value.

[0069] It will further be appreciated that the OR operation reduces the complexity of each subtraction operation from O(N) to 0(1).

[0070] Reference is now made to Fig. 8, which shows an alternative embodiment of the present invention which uses a variable RESULT to store the bits as they are being determined, but as shifted squared locations of each bit bi. Thus, at the beginning of the ith iteration, variable RESULT will have the (i+1 )th bit in the 2i+2 location, the (i+2)th bit in the 2i+3 location, and so on.

[0071] In this embodiment, step 38 is followed by step 39, where CPU 10 adds a 1 to the (2i+l)th location since variable TEST is positive. Then CPU 10 shifts (step 41) variable RESULT right by 1 bit location. In step 43, CPU 10 updates variable CHECK to the value of variable RESULT. In this manner, at the end of the iterations, variable RESULT will be shifted from its wide state holding the number of bits in variable X (32 bits in the example above) to its square root state (16 bits in this example) and, in the square root state it will store the results (i.e., square root B).

[0072] Reference is now made to Fig. 9, which shows a table of the values of the bits of variable CHECK at the end of iterations 15 - 0. The columns hold the bits, listed from bit 31 to bit

0, and the rows store the variable CHECKi, listed as Ci, from C15 to CO. To begin with (i.e., at C15 when i=l 5), variable CHECK stores the check value of 1 in the 30 ^th bit location. In the next iteration (at C14), variable CHECK stores bit value bis in the 29 ^th location and the check value of 1 in the 28 ^th bit location. After the final iteration and the final shift right, variable CHECK contains the final result value, listed in a RESULT (i.e., RES) row.

[0073] Applicant has noted that, for the first 8 iterations (i.e., C 15 - C8), there is no data in the lower part of variable CHECK (i.e., in bits 15 - 0). Therefore, the lower bits do not have to be included in the subtraction operation until C7.

[0074] Similarly, for the final 8 iterations, there is no data in the upper part of variable CHECK (i.e., in bits 24 - 31), due to the shifting. Therefore, the higher 8 bits do not have to be included in the subtraction operation after C7. Instead, at this point, CPU 10 may include the lower bits (i.e., bits 0 - 15) and the middle bits (16 - 23) in the subtraction operation.

[0075] However, it is typically very difficult for a CPU, such as CPU 10, to perform bit-wise operations and thus, CPU 10 cannot easily include only the upper or only the middle and lower bits in a subtraction operation. Moreover, it is especially difficult for a CPU to do so on a plurality of values at one time.

[0076] Applicant has realized that the proposed method and system is particularly efficient when performed on an associative processing unit (APU), such as the Gemini, commercially available from GSI Technology Inc. As described in US patents, US 8,238,173, entitled “Using Storage Cells to Perform Computation”, US 9,418,719 entitled “In-Memory Computational Device”, and US 9,558,812, entitled “SRAM Multi-Cell Operations”, all assigned to the common assignee of the present invention and incorporated herein by reference, the APU operates separately on each bit and thus, can easily operate on only some of the bits, such as only on the upper bits or only on the middle and lower bits of the variables PREV and CHECK. Furthermore, the APU operates on 32K values in parallel, and can thus perform addition and subtraction on selected bits of multiple numbers at the same time. [0077] Reference is now briefly made to Fig. 10, which illustrates an exemplary portion of an

APU 48 which comprises an associative memory array 50, a multiple row decoder 52, a multiple column decoder 54 and a controller 56. Associative memory array 50 may be divided into a multiplicity of sections 68, of which Fig. 10 shows only 2 exemplary sections 68. Each section 68 has a plurality cells 58 arranged in rows 60 and columns 62. The cells 58 in a row 60 are connected by a word line 66 capable of activating cells in multiple columns 62.

[0078] A number to be operated upon is stored in one column 62 and there are typically 32K columns 62 storing 32K numbers. The cells 58 in a column 62 are connected by a bit line processor 64, connected to multiple column decoder 54, capable of enabling computation on its column 62. Each column 62 is divided into multiple sections 68 and typically, each section operates on a single bit of a multi-bit number stored in the column.

[0079] Unique to APUs, multiple row decoder 52 may activate multiple rows 60 concurrently and multiple column decoder 54 may activate multiple columns 62 concurrently, in each section 68. Decoders 52 and 54 are controlled by controller 56 to implement desired methods and algorithms. Each column 62 of each section 68 may perform the needed computation for a single bit and activating multiple columns of the same section 68 results in concurrent computation of the same bit but of multiple numbers.

[0080] Since each section 68 is separately operatable, APU 48 operates separately on each bit and thus, can select which sections of variables PREV and CHECK to operate at any time.

[0081] It will be appreciated that the method and system described hereinabove can be implemented on numbers, or vectors, with more than the standard 32 bits. Since most working spaces are divided into 16-bit partitions, then a calculation on a 48-bit vector may have three partitions - a high partition, a middle partition and a lower partition. At the beginning, controller 56 implements operations only on the high partition. After 16 bits, controller 56 adds the middle partition until the method no longer works on any bits in the high partition. At this point, controller 56 adds the lower partition . Thus, for a number that contains more than 32 bits, there is a point where the subtraction no longer operates on the high partition.

[0082] It will be appreciated that the present invention provides an efficient method for computing the square root of a number. Moreover, when implemented on an associative memory device, it may concurrently and efficiently compute the square root of multiple numbers.

[0083] Applicant has also realized that building the square root from the left side (using the square value of a guess) and shifting the result right in each iteration (to get the square value of the current guess) reduces the complexity of the square root computation for N-bit number X from O(N ² ) to O(N). In addition, since the operands are disjoint, APU 48 implements the addition operation with an OR operation, which is a single cycle operation on APU 48, as opposed to the addition operation which takes 12 cycles for 32K elements. This reduces the complexity of each addition from O(N) to 0(1).

[0084] It will also be appreciated that, in APU 48, the update operation (i.e., steps 42, 44 and 46 of Fig. 7) can be performed in one cycle. For the 13 ^th bit of the example, this may involve shifting right bits bis, bu from locations 29 and 28 to locations 28 and 27 by writing bit bis to location 28, bit bu to location 27 and a 0 to location 29 and, at the same time, if the result is false (i.e. bi3 is 0), write a 0 to location 26.

[0085] While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.