LIN JENN-YU G (CN)
LU RUI-HONG (CN)
YANG TA-YUNG (CN)
LIN JENN-YU G (CN)
LU RUI-HONG (CN)
| SU1640717A1 | 1991-04-07 | |||
| EP0840456A2 | 1998-05-06 | |||
| JP2001045754A | 2001-02-16 | |||
| US5910745A | 1999-06-08 |
| 1. | A multiplierdivider circuit comprising: a first multiplier input terminal, for receiving a first multiplier input signal; a second multiplier input terminal, for receiving a second multiplier input signal; a divisor input terminal, for receiving a divisor input signal; an output voltage terminal, for generating an output voltage signal; a pulse generator, for generating a pulse signal, a sampling signal, and a clear signal; a sawtooth signal generator, for generating a sawtooth signal in response to said divisor input signal, wherein the period of said sawtooth signal is fixed, and wherein a maximum voltage and a slew rate of said sawtooth signal are proportional to said divisor input signal; a chargetime control circuit, for generating a chargetime signal to produce a programmable charge time, wherein said sawtooth signal is compared with said first multiplier input signal to produce said chargetime signal; a linear charging circuit having a charge circuit for generating an outputstage signal, wherein a chargetime of said linear charging circuit is determined by said programmable charge time; and a samplehold circuit, for sampling said outputstage signal and producing said output voltage signal at said output voltage terminal of the multiplierdivider circuit. |
| 2. | The multiplierdivider circuit as claimed in claim 1, wherein the magnitude of said output voltage signal of the multiplierdivider circuit is substantially proportional to the product of the magnitude of said first multiplier input signal and the magnitude of said second multiplier input signal. |
| 3. | The multiplierdivider circuit as claimed in claim 1, wherein the magnitude of said output voltage signal of the multiplierdivider circuit is inversely proportional to the magnitude of said divisor input signal. |
| 4. | The multiplierdivider circuit as claimed in claim 1, wherein said sawtooth signal generator comprises: a first sawtooth input terminal, for receiving said pulse signal; a second sawtooth input terminal, for receiving said divisor input signal; a sawtooth output terminal, for generating said sawtooth signal; a sawtooth capacitor, connected between said sawtooth output terminal and the ground reference; a sawtooth current sink, for discharging said sawtooth capacitor, wherein said sawtooth current sink has an output connected to the ground reference, and wherein said sawtooth current sink has a modulated terminal connected to said second sawtooth input terminal; a sawtooth inverter, having an input connected to said first sawtooth input terminal; a sawtooth discharge switch, connected between said sawtooth output terminal and an input of said sawtooth current sink, wherein said sawtooth discharge switch has a control terminal connected to an output of said sawtooth inverter; and a sawtooth charge switch, connected between said second sawtooth input terminal and said sawtooth output terminal, wherein said sawtooth charge switch has a control terminal connected to said first sawtooth input terminal. |
| 5. | The multiplierdivider circuit as claimed in claim 4, wherein said sawtooth current sink comprises: a sawtooth transistor, for producing a discharge current; a sawtooth amplifier, having an output terminal for controlling said sawtooth transistor, wherein said sawtooth amplifier has a negative input connected to a source of said sawtooth transistor, and wherein said sawtooth amplifier has a positive input connected to said second sawtooth input terminal; and a sawtooth resistor connected between said source of said sawtooth transistor and said output of said sawtooth current sink. |
| 6. | The multiplierdivider circuit as claimed in claim 4, wherein the discharge time of said sawtooth capacitor is constant while the magnitude of said divisor input signal varies. |
| 7. | The multiplierdivider circuit as claimed in claim 4, wherein the peak value of said sawtooth signal is proportional to the magnitude of said divisor input signal. |
| 8. | The multiplierdivider circuit as claimed in claim 1, wherein the chargetime control circuit comprises: a chargetime comparator, wherein said chargetime comparator has a positive input connected to said first multiplier input terminal and wherein said chargetime comparator has a negative input supplied with said sawtooth signal; a pulse inverter, for inverting said pulse signal; and an ANDgate, for generating said chargetime signal, wherein said ANDgate has a first input connected to an output of said chargetime comparator, and wherein said ANDgate has a second input connected to an output of said pulse inverter. |
| 9. | The multiplierdivider circuit as claimed in claim 1, wherein the period of said programmable charge time is proportional to the magnitude of said first multiplier input signal divided by the magnitude of said divisor input signal;. |
| 10. | The multiplierdivider circuit as claimed in claim 1, wherein said linear charging circuit comprises: a charge capacitor, for generating said outputstage signal, wherein said charge capacitor is connected to the ground reference; a charge switch, connected between said second multiplier input terminal and said charge capacitor, wherein said charge switch has a control terminal supplied with said chargetime signal; and a discharge switch, connected between said charge capacitor and the ground reference for discharging said charge capacitor, wherein said discharge switch has a control terminal controlled by said clear signal. |
| 11. | The multiplierdivider circuit as claimed in claim 1, wherein the state of the multiplierdivider circuit is refreshed in response to said clear signal and said sampling signal;. |
| 12. | The multiplierdivider circuit as claimed in claim 1, wherein said samplehold circuit comprises: a samplehold amplifier, for buffering said outputstage signal, wherein said samplehold amplifier has a positive input supplied with said first outputstate signal, and wherein said samplehold amplifier has a negative input connected to an output of said samplehold amplifier; a samplehold switch, for sampling said outputstage signal, wherein said samplehold switch is connected between said output of said samplehold amplifier and said output voltage terminal of the multiplierdivider circuit, and wherein said samplehold switch has a control terminal supplied with said sampling signal; and a samplehold capacitor for holding said output signal, wherein said samplehold capacitor is connected between said output voltage terminal of the multiplierdivider circuit and the ground reference. |
| 13. | The multiplierdivider circuit as claimed in claim 1, wherein said pulse generator comprises: a pulse output terminal, for generating said pulse signal; a sample output terminal, for generating said sampling signal; a clear output terminal, for generating said clear signal; a pulsegenerator current source, having an input connected to a voltage source; a pulsegenerator current sink, having an output connected to the ground reference; a pulsegenerator junction; a first pulsegenerator switch, connected between an output of said pulsegenerator current source and said pulsegenerator junction; a second pulsegenerator switch, connected between said pulsegenerator junction and an input of said pulse generator current sink; and a control circuit, for controlling said first pulsegenerator switch and said second pulsegenerator switch. |
| 14. | The multiplierdivider circuit as claimed in claim 13, wherein said control circuit comprises: a hysteresis comparator, wherein said hysteresis comparator has an input connected to said pulsegenerator junction; a pulsegenerator capacitor, connected between said input of said hysteresis comparator and the ground reference; a first array of two NOTgates, having an input connected to the an output of said hysteresis comparator; a pulsegenerator comparator, having a positive input connected to said sawtooth output terminal of said sawtooth signal generator, wherein said pulsegenerator comparator has a negative input connected to a reference voltage terminal ; a second array of two NOTgates, having an input connected to an output of said pulsegenerator comparator; a latch circuit, composed of a first NANDgate and a second NANDgate, wherein said latch circuit has a first input connected to an output of said first array of two NOTgates, wherein said latch circuit has a second input connected to an output of said second array of two NOTgates, and wherein said latch circuit has an output for supplying a clock signal to a control terminal of said second pulsegenerator switch; and a NOTgate, for supplying an inverted clock signal to a control terminal of said first pulsegenerator switch, wherein said NOTgate has an input connected to said output of said latch circuit. |
| 15. | The multiplierdivider circuit as claimed in claim 13, wherein said control circuit further comprises: a third array of three NOTgates, having an input connected to said output of the latch circuit; a first pulsegenerator ANDgate, having an input connected to an output of said third array of three NOTgates, wherein said first pulsegenerator ANDgate has an inverted input connected to said output of said latch circuit, and wherein said first pulsegenerator ANDgate has an output connected to said sample output terminal; a fourth array of three NOTgates, having an input connected to said first input of said latch circuit; a second pulsegenerator ANDgate, having an input connected to an output of said fourth array of three NOTgates, wherein said second pulsegenerator ANDgate has an inverted input connected to said first input of said latch circuit, and wherein said second pulse generator ANDgate has an output connected to said clear output terminal of said pulse generator; and a third NANDgate, having a first input connected to said output of said latch circuit, wherein said third NANDgate has a second input connected to said first input of said latch circuit, and wherein said third NANDgate has an output connected to said pulse output terminal of said pulse generator. |
| 16. | The multiplierdivider circuit according to claim 1, wherein said sampling signal is generated in response to said pulse signal, following a first delay time, wherein said clear signal is generated in response to said sampling signal, following a second delay time. |
| 17. | The multiplierdivider circuit according to claim 1, wherein the multiplierdivider circuit is constructed of CMOS MOSFETbased devices. |
| 18. | A method of circuit operation in multiplierdivider circuit, comprising: receiving a first multiplier input signal; receiving a second multiplier input signal; receiving a divisor input signal; generating a pulse signal; generating a sampling signal in response to said pulse signal following a first delay time; generating a clear signal, in response to said sampling signal following a second delay time; generating a sawtooth signal in response to said pulse signal, wherein the peak value of said sawtooth signal is proportional to the magnitude of said divisor input signal, and wherein the period of said sawtooth signal is constant; charging a capacitor for generating an outputstage signal, wherein said capacitor is charged by a current with an amplitude proportional to the magnitude of said second multiplier input signal; controlling a charge time of said capacitor, wherein said charge time of said capacitor is proportional to the magnitude of said first multiplier input signal, wherein a charge time of said capacitor is inversely proportional to the magnitude of said divisor input signal; discharging said capacitor for refreshing the state of the multiplierdivier circuit; and sampling and holding said outputstage signal to produce an output voltage signal. |
| 19. | The method of circuit operation in the multiplierdivider circuit as claimed in claim 18, wherein the magnitude of said output voltage signal of the multiplierdivider circuit is substantially proportional to the magnitude of said first multiplier input signal multiplied by the magnitude of said second multiplier input signal. |
| 20. | The method of circuit operation in the multiplierdivider circuit as claimed in claim 18, wherein the magnitude of said output voltage signal of the multiplierdivider circuit is inversely proportional to the magnitude of said divisor input signal. |
BACKGROUND OF THE INVENTION There are many uses of analog multiplier-dividers in modern electronics.
Multiplier-dividers produce an output signal that is proportional to a ratio of two or more input signals. The input and output signals can either be voltages or currents.
One common use for multiplier-dividers is in power factor correction (PFC) circuits. PFC circuits commonly use multiplier-dividers to generate a control signal based on an input current, a feedback signal, and an input voltage. Other uses of multiplier-divider circuits include but are not limited to automatic gain control (AGC) circuits.
There are many known ways of constructing analog multiplier-dividers, such as logarithmic amplifiers and antilog amplifiers. The implementation of a logarithmic amplifier normally uses the p-n junction volt-ampere characteristic; it is given by ! o-) ox [exp (VD/nVT)-l]----------- (l) where Io is the reverse saturation current; VD is the forward bias voltage; is the constant; VT = T/11,600 and T is the temperature °K. Since the output current In is the exponential function of the forward bias voltage VD, the linear operating region is small. The book"Analog Integrated Circuit Design"by David A. Johns and Ken Martin (1997, p 366-367) teaches another known analog multiplier-divider. This particular multiplier-divider is also implemented by using p-n junction devices. As FIG. 1 shows, it is referred to as a four-quadrant multiplier.
The prior-art multiplier-divider shown in FIG. 1 is built using bipolar transistor devices. It supplies an output current with the amplitude that is proportional to the product of a first input current and a current ratio. The current ratio is equal to the amplitude of a second input current divided by the amplitude of a bias current.
Many other known prior-art multiplier-dividers are all based on the principles as the prior-art multiplier-divider shown in FIG. 1. Those prior-art multiplier-dividers share the same disadvantages because they are built using bipolar transistor devices.
One disadvantage of the prior-art multiplier-divider shown in FIG. 1 is its high manufacture cost. For many present-day applications, such as PFC circuits, integrated circuits manufacture using bipolar process are not suitable because bipolar devices still occupy lots of die space and increase the cost.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is that the output of the circuit varies significantly with temperature. Referring to equation (1), it is obviously that bipolar devices have high temperature coefficients. Thus, the output of the circuit is highly susceptible to temperature changes.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is high power consumption. The prior-art multiplier-divider requires a constant non-zero biasing current to operate bipolar transistors in linear mode. This results in significant power consumption.
Another disadvantage of the prior-art multiplier-divider shown in FIG. 1 is poor noise immunity. This is because the prior-art multiplier-divider uses high-gain bipolar transistor devices. With such devices, even relatively small input signal distortion can result in significant output signal distortion.
Another disadvantage of the prior-art multiplier-divider of FIG. 1 is that it has a narrow input range, limited to the linear operating region of bipolar transistors.
Outside this narrow input signal range, the multiplier-divider shown in FIG. 1 is highly susceptible to distortion.
Therefore, it is needed to improve the drawbacks of the prior-art multiplier-dividers. In particular, an improved multiplier-divider that has a smaller die size while being suitable for a wider range of operating temperatures is absolutely needed.
SUMMARY OF THE INVENTION According to one aspect of the present invention, the multiplier-divider of the present invention produces an output signal in response to three input signals. The output signal is proportional to the product of a first input signal and a second input signal divided by a third input signal.
A general objective of the present invention is to provide a general-purpose multiplier-divider. It is a further objective of the present invention to provide a multiplier-divider that is suitable to apply in a power factor correction (PFC) circuit of a switch mode power supply.
Another objective of the present invention is to provide a multiplier-divider that is manufactured in CMOS process. The multiplier-divider according to the present invention exclusively uses MOSFET-based devices. Therefore, the multiplier-divider according to the present invention can be manufactured at a significantly reduced die-size level, and at a lower cost than the prior-art multiplier-divider.
Another objective of the present invention is to provide a multiplier-divider having a characteristic equation that is substantially independent of temperature, compared to prior-art multiplier-dividers.
Another objective of the present invention is to provide a multiplier-divider with reduced power consumption. The multiplier-divider according to the present invention does not require a constant biasing current.
Another objective of the present invention is to provide a multiplier-divider with improved noise immunity. The accuracy of the output signal of the multiplier-divider according to the present invention is not significantly affected by small noise components from the input signals.
Briefly, the present invention relates to a switched charge multiplier-divider. The switched charge multiplier-divider is built according to the principle of capacitor charge theory. The voltage across the capacitor is proportional to the product of the charge current and the charge time interval, and is divided by the capacitance of the capacitor. By using a modulated charge current and a programmable charge time to switch the capacitor, the voltage across the capacitor can be controlled. This capacitor voltage is the output voltage of the switched charge multiplier-divider.
The switched charge multiplier-divider according to the present invention can perform signal multiplication and division. Use of the capacitor charge technique enables the implementation of a multiplier-divider with reduced power consumption, improved noise immunity, a wider operating range, and a lower temperature coefficient.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 shows a conventional multiplier-divider.
FIG. 2 shows a block diagram of a switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 3 shows the switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 4 shows a sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 5 shows a dynamic current sink of the sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 6 shows a pulse generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 7 shows a timing diagram of the sawtooth signal generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention.
FIG. 8 shows a timing diagram of the pulse generator of the switched charge multiplier-divider according to a preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings wherein the contents are for purposes of illustrating preferred embodiments of the invention only and not for purposes of limiting same.
FIG. 1 shows a prior-art multiplier-divider. The prior-art multiplier-divider is constructed of an array of six bipolar transistors 10,11, 12,13, 14 and 15. A base of each of the transistors 10,11, 12,13, 14 and 15 are all tied together.
A collector of the transistor 10 is connected to the base of the transistor 10. An emitter of the transistor 10 is connected to the ground reference. The collector of the transistor 10 is connected to a first positive input terminal. A collector of the transistor 11 is connected to a negative output terminal. A collector of the transistor 12 is connected to a positive output terminal. A collector of the transistor 13 is connected to the negative output terminal. An emitter of the transistor 12 and an emitter of the transistor 13 are connected to a second positive input terminal. A collector of the transistor 14 is connected to the positive output terminal. An emitter of the transistor 11 and an emitter of the transistor 14 are connected to a second negative input terminal. A collector of the transistor 15 is connected to a first negative input terminal.
The collector of the transistor 15 is connected to the base of the transistor 15. An emitter of the transistor 15 is connected to the ground reference. Operation of this circuit will be well known to those skilled in the art and does not need to be discussed in further detail herein.
As discussed above, one major drawback of this prior-art multiplier-divider is that it is constructed of bipolar transistor devices. This results in a large die-size and introduces high temperature dependence into the characteristic of the prior-art multiplier-divider.
To overcome these problems, the present invention proposes a switched charge multiplier-divider 100 constructed of MOSFET devices. FIG. 2 shows a block diagram of the switched charge multiplier-divider 100 according to the present invention. The switched charge multiplier-divider 100 has a first multiplier input terminal for receiving a first multiplier input signal VB, a second multiplier input terminal for receiving a second multiplier input signal IA, and a divisor input terminal for receiving a divisor input signal Vc. The switched charge multiplier-divider 100 also has an output terminal for generating an output voltage signal VM. The magnitude of the output voltage signal VM is proportional to the magnitude of the first multiplier input signal Vs multiplied by the magnitude of the second multiplier input signal IA, divided by the divisor input signal Vc. The first multiplier input signal Va and the divisor input signal Vc are voltage signals and the second multiplier input signal IA is a current signal. The output of the switched charge multiplier-divider 100 can be expressed as, <BR> <BR> <BR> <BR> VM α k#(IA#VB) ------------------------------------<BR> <BR> <BR> <BR> Vc where k is an constant.
However, it is to be understood that voltage input/output could be converted to current input/output, and that current input/output could be converted to voltage input/output without departing from the spirit of the invention. Methods of converting a current to a voltage, and vice-versa, are well known to those skilled in the art.
The switched charge multiplier-divider 100 is implemented according to the principle of capacitor charge theory. An important equation describing the behavior of capacitors is : Q = C # V = ##T ------------------------------------ (3) where Q is the charge, C is the capacitance of the capacitor, V is the voltage across the capacitor, I is the charge current, and T is the charge time.
According to equation (3), a programmable charge time Tl can be expressed as, T1 = VB x CI ------------------------------------ I1 where a charge current Il charges a capacitor that has a capacitance Cl.
Vc Ri Then equation (4) can also be shown as, T1=RI x C1 x VB ------------------------------------ Vc Charging a capacitor with a capacitance C2 with the second multiplier input signal IA for the duration of the programmable charge time Tl will produce the output voltage signal VM at the output of the multiplier-divider 100, <BR> <BR> <BR> <BR> IA Ci IA X VB IA X VB<BR> <BR> Vm-x Ti-x Ri x = k x<BR> <BR> C2 C2 Vc Vc where Rl is the resistance of the resistor, Cl and C2 are the capacitances of the capacitors, k is a constant equal to Rl x (Cl/C2).
Therefore, a basic model of the multiplier-divider is built as described above.
FIG. 3 shows a preferred embodiment of the switched charge multiplier-divider 100 according to the present invention. The switched charge multiplier-divider 100 includes a sawtooth signal generator 110, a charge-time control circuit 120, a linear charging circuit 130, a sample-hold circuit 140, and a pulse generator 200. The sawtooth signal generator 110 generates a sawtooth signal VSAW that has a fixed period. The maximum voltage and the slew rate of the sawtooth signal VSAW are proportional to the magnitude of the divisor input signal Vc. The sawtooth signal VSAW is compared with the first multiplier input signal Va to generate a charge-time signal VCT. The charge-time signal VCT determines the programmable charge time Tl of the charge-time control circuit 120. The programmable charge time T is thus controlled by the divisor input signal Vc and the first multiplier input signal Va. The linear charging circuit 130 includes a charge circuit that is charged by the second multiplier input signal IA. The charge time of the linear charging circuit 130 is determined by the programmable charge time Tl. The sample-hold circuit 140 samples an output-stage signal Vc2 of the linear charging circuit 130 and holds the output voltage signal VM at the output terminal of the switched charge multiplier-divider 100.
The pulse generator 200 produces control signals including a pulse signal PLS, a sampling signal SMP and a clear signal CLR. As FIG. 8 shows, the sampling signal SMP follows the pulse signal PLS after a delay time tot. The clear signal CLR follows the sampling signal SMP after a delay time tD2.
FIG. 6 shows the pulse generator 200 according to a preferred embodiment of the present invention. The pulse generator 200 includes a current source 210, a switch 211, a switch 212, and a current sink 213. The pulse generator 200 further includes a capacitor 220, a hysteresis comparator 221, a NOT-gate 222, a NOT-gate 223. The pulse generator 200 further includes a comparator 230, a NOT-gate 231, a NOT-gate 232, a NAND-gate 240, a NAND-gate 241, and a NOT-gate 242. The pulse generator 200 further includes a NOT-gate 250, a NOT-gate 251, a NOT-gate 252, and an AND-gate 253. The pulse generator 200 further includes a NOT-gate 260, a NOT-gate 261, a NOT-gate 262, an AND-gate 263, and a NAND-gate 270.
An input of the current source 210 is connected to a voltage source V DD. The switch 211 is connected between an output of the current source 210 and an input junction. The switch 212 is connected between the input junction and an input of the current sink 213. An output of the current sink 213 is connected to the ground reference. An input of the hysteresis comparator 221 is connected to the input junction.
The capacitor 220 is connected between the input of the hysteresis comparator 221 and the ground reference. An output of the hysteresis comparator 221 is connected to an input of the NOT-gate 222. An output of the NOT-gate 222 is connected to an input of the NOT-gate 223. A voltage terminal VR is connected to an output of the NOT-gate 223.
A positive input of the comparator 230 is connected to an output terminal of the sawtooth signal generator 110 for receiving the sawtooth signal VSAW. A negative input of the comparator 230 is supplied with a reference voltage VREF. An output of the comparator 230 is connected to an input of the NOT-gate 231. An output of the NOT-gate 231 is connected to an input of the NOT-gate 232. An output of the NOT-gate 232 is connected to a voltage terminal Vs.
A first input of the NAND-gate 240 is connected to the output of the NOT-gate 223. A second input of the NAND-gate 240 is connected to an output of the NAND-gate 241. A first input of the NAND-gate 241 is connected to an output of the NAND-gate 240. A second input of the NAND-gate 241 is connected to the output of the NOT-gate 232. The output of the NAND-gate 240 outputs a clock signal CKl, which is supplied to a control terminal of the switch 212. The clock signal CK, is also supplied to a control terminal of the switch 211 via the NOT-gate 242.
An input of the NOT-gate 250 is connected to the output of the NAND-gate 240 for receiving the clock signal CKl. An input of the NOT-gate 251 is connected to an output of the NOT-gate 250. An input of the NOT-gate 252 is connected to an output of the NOT-gate 251. An output of the NOT-gate 252 is connected to an input of the AND-gate 253. An inverted input of the AND-gate 253 is connected to the output of the NAND-gate 240. The AND-gate 253 of the pulse generator 200 outputs the sampling signal SMP.
An input of the NOT-gate 260 is connected to the voltage terminal VR. An input of the NOT-gate 261 is connected to an output of the NOT-gate 260. An input of the NOT-gate 262 is connected to an output of the NOT-gate 261. An output of the NOT-gate 262 is connected to an input of the AND-gate 263. An inverted input of the AND-gate 263 is connected to the voltage terminal VR. The AND-gate 263 of the pulse generator 200 outputs the clear signal CLR.
A first input of the NAND-gate 270 is connected to the output of the NAND-gate 240. A second input of the NAND-gate 270 is connected to the voltage terminal VR.
The output of the NAND-gate 270 of the pulse generator 200 outputs the pulse signal PLS.
FIG. 8 is a timing diagram illustrating the operation of internal signals and output signals generated by the pulse generator 200. The operation of this circuit will be well known to those skilled in the art and therefore detailed description thereof is not included herein.
When the pulse generator 200 generates the pulse signal PLS, the sawtooth signal generator 110 will output a sawtooth signal VSAW in response to the divisor input signal Vc. After the pulse signal PLS goes low, the charge-time control circuit 120 will compare the sawtooth signal VSAW with the first multiplier input signal Vs to produce a charge-time signal VCT. The programmable charge time Tl of the charge-time signal VCT will be proportional to the magnitude of the first multiplier input signal Vs divided by the divisor input signal Vc. The linear charging circuit 130 will charge a capacitor 131 for the duration of the programmable charge time TI. The capacitor 131 will be charged by a current having an amplitude proportional to the magnitude of the second multiplier input signal IA. At this point, the charge of the capacitor 131 will determine the magnitude of the output voltage signal VM of the switched charge multiplier-divider 100. When the pulse generator 200 supplies the sampling signal SMP, the output-stage signal Vc2 of the linear charging circuit 130 will be sampled by the sample-hold circuit 140 to produce the output voltage signal VM of the multiplier-divider 100. The delay time tD2 is inserted between the falling-edge of the sampling signal SMP and the rising-edge of the clear signal CLR to reset the switched charge multiplier-divider 100.
FIG. 4 shows the sawtooth signal generator 110 according to a preferred embodiment of the present invention. The sawtooth signal generator 110 includes a switch 111, a NOT-gate 112, a switch 113, a capacitor 114 having a capacitance Cl, and a dynamic current sink 115. A control terminal of the switch 111 and an input of the NOT-gate 112 are supplied with the pulse signal PLS of the pulse generator 200.
An output of the NOT-gate 112 is connected to a control terminal of the switch 113.
The switch 111 is supplied with the divisor input signal Vc and is connected to the output terminal of the sawtooth signal generator 110. The capacitor 114 is connected between the output terminal of the sawtooth signal generator 110 and the ground reference. The switch 113 is connected between the output terminal of the sawtooth signal generator 110 and an input of the dynamic current sink 115. An output of the dynamic current sink 115 is connected to the ground reference. A modulated terminal of the dynamic current sink 115 is supplied with the divisor input signal Vc.
As the pulse generator 200 supplies a logic-high pulse signal PLS, the switch 111 will close. This will cause the divisor input signal Vc to charge the capacitor 114.
When the pulse signal PLS goes low, the switch 111 will open, and the switch 113 will close. At this point, the capacitor 114 will begin to discharge via the dynamic current sink 115. To ensure that the discharge time will be independent of the divisor input signal Vc, the dynamic current sink 115 generates a sink current I1 that is proportional to the magnitude of the divisor input signal Vc. Therefore the maximum voltage and the slew rate of the sawtooth signal VSAW will be proportional to the magnitude of the divisor input signal Vc.
FIG. 5 shows the dynamic current sink 115 according to a preferred embodiment of the present invention. The dynamic current sink 115 generates the sink current Il that is proportional to the magnitude of the divisor input signal Vc. This is used to regulate the discharge time of the capacitor 114, so that the period length of the sawtooth signal VSAW will be independent of the magnitude of the input signals of the switched charge multiplier-divider 100.
The dynamic current sink 115 includes an operational amplifier 116, a resistor 117 having a resistance Rl, and a MOSFET 118. A positive terminal of the operational amplifier 116, which is also the modulated terminal of the dynamic current sink 115, is supplied with the divisor input signal Vc. A negative terminal of the operational amplifier 116 is connected to a source of the MOSFET 118. A drain of the MOSFET 118, which is also the input of the dynamic current sink 115, is connected to the output terminal of the switch 113 shown in FIG. 4. A first terminal of the resistor 117 is connected to the source of the MOSFET 118. A second terminal of the resistor 117, which is also the output of the dynamic current sink 115, is connected to the ground reference. An output terminal of the operational amplifier 116 is connected to a gate of the MOSFET 118. The dynamic current sink 115 generates the sink current Il that is proportional to the magnitude of the divisor input signal Vc, divided by the resistance Rl of the resistor 117. Operation of this circuit will be well known to those skilled in the art and therefore a detailed description thereof is not included herein.
Referring to FIG. 3, the output terminal of the sawtooth signal generator 110 supplies the sawtooth signal VSAW to the charge-time control circuit 120. The charge-time control circuit 120 includes a comparator 121, an AND-gate 122, and a NOT-gate 123.
A negative terminal of the comparator 121 is connected to the output terminal of the sawtooth signal generator 110. The first multiplier input signal Va is supplied to a positive terminal of the comparator 121. An output of the comparator 121 is connected to a first input terminal of the AND-gate 122. A second input terminal of the AND-gate 122 is connected to an output of the NOT-gate 123. The pulse signal generator 200 supplies the pulse signal PLS to an input of the NOT-gate 123. An output of the AND-gate 122 generates the charge-time signal VCT to determine the programmable charge time T.
The comparator 121 will compare the first multiplier input signal VB with the sawtooth signal VSAW of the sawtooth signal generator 110. When the pulse signal r PLS supplied by the pulse signal generator 200 goes low, the AND-gate 122 will output a charge-time signal VCT, in which the on-time of said charge-time signal VCT is proportional to the magnitude of the first multiplier input signal Vs.
The charge-time signal VCT is supplied to the linear charging circuit 130. The linear charging circuit 130 includes a capacitor 131 has the capacitance C2, a switch 132, and a switch 133.
An input terminal of the linear charging circuit 130 is supplied with the second multiplier input signal IA of the switched charge multiplier-divider 100. The switch 132 is connected between the input terminal of the linear charging circuit 130 and an output terminal of the linear charging circuit 130. A control terminal of the switch 132 is connected to the output of the AND-gate 122. A turn-on time t, 32 of the switch 132 will be proportional the product of the resistance R, of the resistor 117, the capacitance Cl of the capacitor 114, and the magnitude of the first multiplier input signal VB. The turn-on time tl32 of the switch 132 will be inversely proportional to the magnitude of the divisor input signal Vc. The switch 133 is connected between the output terminal of the linear charging circuit 130 and the ground reference. The pulse generator 200 supplies the clear signal CLR to a control terminal of the switch 133.
The capacitor 131 is connected between the output terminal of the linear charging circuit 130 and the ground reference.
When the switch 132 is closed by the charge-time signal VCT supplied by the AND-gate 122, the second multiplier input signal IA of the switched charge multiplier-divider 100 will supply a current to charge the capacitor 131. The amplitude of this current will be proportional to the magnitude of the second multiplier input signal IA. When the pulse generator 200 generates a logic-high clear signal CLR, the switch 133 will close, and the charge stored in the capacitor 131 will be discharged.
The sample-hold circuit 140 includes an operational amplifier 141, a switch 142, and a capacitor 143. A positive input of the operational amplifier 141 is connected to the output terminal of the linear charging circuit 130. A negative input of the operational amplifier 141 is connected to an output of the operational amplifier 141.
The switch 142 is connected between the output of the operational amplifier 141 and the output of the switched charge multiplier-divider 100. A control terminal of the switch 142 is controlled by the sampling signal SMP of the pulse generator 200. The capacitor 143 is connected between the output of the switched charge multiplier-divider 100 and the ground reference.
The operational amplifier 141 is a buffer for the charge of the capacitor 131.
When a logic-high sampling signal SMP from the pulse generator 200 closes the switch 142, the voltage at the output of the operational amplifier 141 will be equal to the potential of the capacitor 131. The maximum voltage of the capacitor 131 will determine the output voltage signal VM at the output of the switched charge multiplier-divider 100. Within a constant factor, the magnitude of this output voltage signal VM will be proportional to the magnitude of the first multiplier input signal VB multiplied by the magnitude of the second multiplier input signal IA, divided by the magnitude of the divisor input signal Vc. The capacitor 143 is included as a holding capacitor to keep the output voltage signal VM.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims or their equivalents.