CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Application No. 63/385,572. filed November 30, 2022, entitled “TEST PATTERN VECTORS IN HOMOGENOUS MULTI-DIE PACKAGES”, which is hereby incorporated herein by reference in its entirety for all purposes.

FIELD OF THE INVENTION

[0002] One or more embodiments disclosed relate to testing integrated circuits (ICs). and more particularly, to Inter-Chip scan testing with data delivery to homogenous dies using one or more pipelines configured to enable vector depth and test time optimization.

BACKGROUND

[0003] Semiconductor integrated circuits (ICs) are manufactured using a multi-phase process, packaging generally refers to the process of mounting or placing dies (i.e., “tiles” as referred to herein) within plastic, ceramic, or other packages that facilitate use of multiple tiles packaged in a device. Normally each die is individually tested since the packaged device has heterogenous dies.

[0004] Typically, ICs are characterized in terms of performance. Performance can be measured in terms of whether the IC is able to perform within established design requirements relating to operating frequency, signal fidelity, signal response, or the like. Performance analysis identifies ICs that do not meet minimum design requirements. ICs include sequences of combinatorial logic that are made up of thousands of logic gates, latches, and the like. Scan chain tests are utilized to load the combinatorial logic gates with a known automated test pattern (ATP), the outputs of which are analyzed against known results to determine if one or more faults exist within the combinatorial logic. Faults in an IC may include one or more of stuck-at faults, transistor faults, bridging faults, open faults, delay faults, and the like.

[0005] Test costs are influenced by volume of the patterns (i.e., vector depth) to store in tester memory, speed of shift-in/ out of bits through scan chains (i.e.. flip -flops), i.e.. shift clock frequency. ATE (Automatic Test Equipment) works on a cycle accurate manner (e g., 10 ns) fixed cycles, with all the inputs driven with respect to clock cycles. At the same time, response from the device is monitored (i.e.. strobing) on outputs; output is always monitored with latency interims of cycles, that depends on scan chain length. Electronic Design Automation (EDA) tools accordingly generate patterns with Automatic Test Pattern Generation (ATPG) enabling test scans.

BRIEF SUMMARY

[0006] Embodiments are described here for accessing and testing inner tiles (or dies) within packaged multi-chip-module (MCM) devices that have limited input/output (I/O) for use by testing equipment, where all the tiles are interconnected on package substrate to reduce costs with compliant specifications. Costs associated with production tests involve storage capacity for storing test vectors in addition to the duration for which the test equipment is in use. Emboidments described herein address ATPG Scan Pattern vector depth by reusing the same pattern set to test all tiles (or same dies), which reduces the amount of memory required to save the test patterns. Further, by using scan chain latches between the dies of a multi-die MCM, a higher ATPG scan shift mode frequency may be used, which reduces total test time of testing all tiles during production of packaged device with multiple tiles. Dynamically configuring scan chain pipeline registers among the serially-connected homogenous dies allows the reuse of the same pattern set irrespective of which die is under test, thereby saving vector memory depth, which in turn lowers the packaged device test costs in production. Similarly, configurable scan chain pipeline registers allow an increased ATPG shift mode frequency (i.e., higher frequency, a shorter time-period), to reduce the actual time spent and thereby reduce the associated device test costs in production to test each device.

[0007] Briefly summarized, the MCM system architecture and inter-chip selective test vector scanning methodology of homogenous dies packaged in MCM devices is employed using limited accessible pins in combination with reconfigurable input scan chain pipeline registers. A die-to- die interconnect with wire pass-throughs are used to select inter-die channels between each of the dies. Automated test pattern (ATP) testing vectors are loaded to scan chains of each circuit die throughout the MCM with the same ATP data and timing constraints by configuring a predetermined number of clock cycles via a delay value adjustment of the reconfigurable input pipeline registers, and the die-to-die interconnect. A described testing method configures a first die input pipeline register with a first delay value at a first die of the MCM. ATP data is loaded into a first die scan chain register in a predetermined number of clock cycles via the first delay value of the first die pipeline register, and a scan chain test of the first die is performed with the ATP data. The first die input pipeline register is reconfigured with a second delay value, and the ATP data is loaded into the second die scan chain register in the predetermined number of clock cycles via the second delay value of the first die pipeline register and the die-to-die interconnect, and a scan chain test of the second die is performed. The described method is further extensible to three, four, or more, homogenous dies.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various embodiments in accordance with the present disclosure will be described with reference to the drawings. Same numbers are used throughout the disclosure and figures to reference like components and features.

[0009] FIG. 1 is a block diagram illustrating homogenous dies in a multi-chip-module (MCM) package, for n- dies/ tiles of a multiplicity of n dies having at least one associated reconfigurable pipeline in stage of a multi-die integrated circuit (IC) structure in accordance with an embodiment of the present inventions.

[0010] FIG. 2 shows the Pipeline In/ Out package connections from interconnect dies for Flip- Flop (FF) scan chain in a network illustrating single die, i.e., central block scan chains of a single die of a multi-die IC structure in accordance with the first die (tile) of the FIG. 1 block diagram having homogenous Dies in a package thereof.

[0011] FIG. 3 provides a reconfigurable Inputs Stage for Pipeline Scan Data of a multi-die IC structure to the FF scan chain network of FIG. 2 in accordance with each of the tiles of the FIG. 1 package in accordance with the disclosed embodiments.

[0012] FIG. 4 shows the FF Scan Chains for ATPG test digital logic of each IC device of the multi-tile homogeneous structure of the FIG. 1 having homogenous dies in accordance with each of the tiles of the package.

[0013] FIG. 5 provides a reconfigurable Pipeline Output Stage for the Scan Data of a multi-die IC structure in accordance with the disclosed embodiments.

[0014] FIG. 6A and 6B are a plurality of dies having at least one reconfigurable pipeline in stage associated in a simplified fashion with two (2) identical dies showing channel routing on substrate with pipeline FFs in Scan-In/Out paths the two interconnect dies for the scan chain network IC of a two-die MCM structure thereof.

[0015] FIG. 7 illustrates Ist-die testing of the two (2) identical dies showing channel routing on substrate arrow-highlighted data path targeting scan chain in 1 st die of a two-die MCM structure in accordance with the present embodiments.

[0016] FIG. 8 illustrates 2nd-die testing of the two (2) identical dies showing channel routing on substrate arrow-highlighted data path targeting scan chain in 2nd die of the two-die MCM structure thereof.

DETAILED DESCRIPTION

[0017] FIG. 1 is a block diagram illustrating a selective test vector scanning embodiment for packaged dies of multi-chip-module (MCM) devices, herein multi-die integrated circuit (IC) MCM structure 10. In some embodiments, a MCM may have limited accessible input/output (I/O) pins, and may thereby use reconfigurable input pipeline registers for n- dies/ tiles of a plurality of dies, including a first die 12, and a second die 14. The MCM may include at least one associated reconfigurable input pipeline register 22. Embodiments described herein specifically refer to a plurality of homogenous circuit dies, however, such a constraint should not be considered limiting. The MCM of FIG. 1 further includes a die-to-die interconnect between each of the dies, which may re-purposed from e.g., serial peripheral interface (SPI) applications to convey automated test pattern (ATP) testing vectors. Each circuit die includes a scan chain register, and the ATP testing vectors are loaded to the scan chain registers of selected homogenous dies with the same ATP data and timing provided to the MCM by configuring the reconfigurable input pipeline registers of the respective dies with a specific number of clock cycles via a delay value adjustment to account for delays introduced by the die-to-die interconnect. Homogenous dies use the same ATP data loaded to die scan chains with a defined timing pattern, where each die scan chain can be properly loaded within the same predetermined number of clock cycles, regardless of the particular die location within the set of serially-connected homogenous dies. The plurality of circuit dies may be arranged in a serially-connected hierarchical structure. That is to say, when loading the scan chain register in a selected die, the ATP data is conveyed from an input pipeline register of a first circuit die, over the die-to-die interconnect to an input pipeline register of a second circuit die. and possibly via another die-to-die interconnect to a third circuit die. At least one output pin IC package connection from the MCM connects a die scan out coupling of the multiplicity of dies to a reconfigurable output pipeline register. The MCM structure 10 limited accessible pins may be re-purposed pins for testing.

[0018] The FIG. 1 block diagram employs n- homogenous circuit dies of the hierarchical MCM structure 10 according to the present described embodiment. An IC package 20 includes a multiplicity’ of n dies within the IC package 20, each of dies 12. 14 having at least one associated reconfigurable input pipeline register 22 configured to provide a die scan in coupling 28 to at least one die scan-chain 26. Each of dies 12, 14 further include at least one reconfigurable output pipeline register 24 from a die scan_out coupling 30. At least one input pin IC package connection 16 is provided for loading ATP scan data into the IC package 20 via the reconfigurable input pipeline register 22. The input pin IC package connection 16 may load the ATP scan data into the input pipeline register 22 of a leader circuit die, e g., tile 12, by default. The input pipeline register 22 of the leader circuit die 12 may be selectably configured to couple the ATP scan data into the scan chain 26 on the leader die, or to reroute the ATP scan data over a die-to-die interconnect to follower circuit die 14 to be leaded into the scan chain 36.

[0019] At least one output pin IC package connection 18 is provided from the IC package 20 for outputting the results of the scan chain test, i.e., the captured state of the combinatorial logic after having the scan data loaded. As shown, the output pin IC package connection 18 is connected to the die scan out couplings 30, 34 of one of the multiplicity of n dies via a reconfigurable output pipeline register 34 for selectively communicating the die scan out coupling 30 from a selected one of the multiplicity' of n dies. A die-to-die interconnect 46 having wire pass-throughs 48 establishes a plurality’ of inter-die channels 50 between each of the plurality’ of dies 12. 14 within the IC package 20.

[0020] In some embodiments, the input pipeline register 22 includes multiplexing logic for selectively routing inbound ATP scan data received via input pin 16 to the scan chain 26 within the leader circuit die 12 or to input pipeline registers of a second circuit die of the n homogenous circuit dies. Similarly, multiplexing logic in the output pipeline register 24 may be utilized to selectively output the scan chain results from one of the n homogenous circuit dies, i.e., the scan chain 26 within the leader circuit die 12 or scan chain results 30 received via the die-to-die interconnect 46. An integrated circuit (IC) structure can include an interposer including a plurality of inter-die wires and a first die coupled to the interposer. The first die can include a first output including a first flip-flop coupled to a first inter-die wire of the plurality of inter-die wires and a first input including a second flip-flop coupled to a second inter-die wire of the plurality of interdie wires. The IC may include existing inter-die substrate connections for. e.g., tile-to-tile serial peripheral interface (SPI) communications. Such an inter-die data interface may be re-utilized for the purpose of Scan In/Out data access. Based on the above hardware structures in place, the IC may be configured (i.e., dynamically through device initialization sequence) to apply the ATPG pattern set to the active tile under test. In some embodiments, the configuration of tiles includes how many stages of the pipelines to enable in each tile based on the spread between tiles before applying the ATPG patterns to the tile under test. Latches within each input pipeline register 22 for the follower tiles are configured to latch the ATPG patterns received over the die-to-die interconnect to protect the data against the clock-skew.

[0021] FIG. 2 is a block diagram of circuit die 12. in accordance with some embodiments. As shown, the input and output pipeline register package connections are shown from interconnect dies for Flip-Flop (FF) Scan Chains 26 of the single first die 12 of homogenous dies 12, 14. The scan chains are loaded via the reconfigurable input pipeline register 22 associated with the one or more input pins 16, 16’. FIG. 3 is a schematic for a reconfigurable input pipeline register 22, in accordance with some embodiments. As shown, multiple input pipeline registers 22 associated with input pins 16, 16’ of FIGs. 2 and 3 may be configured in parallel for each homogenous die if multiple input pins are available, but such a constraint should not be considered limiting. As shown, each input pipeline register 22 includes a sequence of flip-flops, each flip-flop having a respective output tap. The flip-flops are configured to apply a configurable delay to the ATP scan data. The input pipeline register 22 further include a multiplexer having a plurality of inputs, each input connected to a respective output tap of the sequence of flip-flops. The multiplexer is configured to receive a select signal, and to select one output tap of the plurality of output taps of the sequence of flip-flops to apply a configurable delay value to the ATP scan data. The delay value selected by the multiplexer may be associated with which homogenous die of the multiplicity of homogenous dies is under test. When circuit dies further down in the hierarchy are under test, the ATP test signal is conveyed through a chain of input pipeline registers. As described above, each input pipeline register includes multiple flip-flop circuits that incrementally progress the ATP test signal. Utilizing a sequence of flip-flop circuits from the input pin to the scan-chain input of the circuit die under test breaks up what would otherwise be a long signal path with a long propagation delay (and thus a slower shift clock rate) into a larger number of smaller paths with small individual propagation delays. As the shift clock rate is dependent on the longest propagation delay, minimizing the maximum propagation delay thus reduces the shift clock rate, which accelerates the scan chain test itself as the scan chain and loading of input pipeline registers is performed using the same clock signal. The die level JTAG IEEE 1149.1 (Joint Test Action Group) standard defines test logic included in the MCM 10 circuit to provide a standardized serial bus test clock signal. In accordance with the JTAG test standard, the clock scan shift frequency may be accelerated to reduce test time. In some alternative embodiments, the clock signal may be supplied directly as routed directly die to die.

[0022] FIG. 4 shows the FF Scan Chains for testing digital logic of each die of the MCM structure 10, in accordance with some embodiments. As shown, each scan-chain includes a sequence of flip-flops. The flip-flops are serially loaded with ATP scan data in a predetermined number of clock cycles in a shift-register manner as described above. The ATP scan data is loaded in parallel to combinatorial logic (not shown) of the MCM and processed via the combinatorial logic using a single clock cycle. The outputs of the combinatorial logic are latched into the scan-chain flops and shifted out at the scan out port 40 for analysis. Multiplexed Scan Style is the industry Standard way of testing Digital circuits for manufacturing defects in Production. Manufacturing defects can be Stuck- At faults where any Standard Cell (like Flop, logic gate) can be Stuck-to GND or Supply during Manufacturing process. Defects can also be due to RC variation of the metals which influence transition of the signal from one state to another. Putting pipeline registers in each die, then as soon as the bit is latched in FF1 of die #1, then changing the signal to the next bit, one can accept the test pattern bit sequence at a faster rate by having these pipeline registers in each die. The increase in frequency of loading serially connected dies is a helpful byproduct of using the pipeline registers.

[0023] FIG. 5 is a schematic of a reconfigurable output pipeline register 24 for the scan data of MCM 10, in accordance with some embodiments. Each homogenous circuit die includes output pipeline register 24 as shown. The processed scan chain data is propagated through each circuit die in the circuit die hierarchy according to delay values similar to the delay values used by the input pipeline registers 22 to load the scan data into the scan chain. For example, if the leader circuit die 12 is currently under test, the output pipeline register 24 of the leader tile is the only output stage in use, and the delay value may be at a highest setting. As circuit dies 14 further down the chain are selected to be the current die under test, the processed scan chain data still progresses through the output pipeline registers 24 of the circuit dies higher up in the circuit die hierarchy. The amount of delay applied by each output pipeline register 24 may decrease proportionally to how many circuit dies are in the overall hierarchy with respect to the current die under test. With the example herein, a Design for Test (DFT) testing of MCM structure 10 multi-die ICs is achieved for multiple homogenous dies within an IC package with the ATPG targeted die testing. DFT testing allows for selecting from a plurality of different available outputs from the input and output pipeline registers to adjust the pipeline registers with a configurable delay value as a way of programming the delay of the first die pipeline register to route the ATP sequence data to a second die in the hierarchy. When testing the second circuit die in the hierarchy, pipeline configuration information is transmitted into the MCM via the input pin to configure the first die input pipeline register 22 with a reduced delay value to account for the delay incurred by propagating the die-to- die interconnect. In such an embodiment, the ATP sequency data is loaded into the scan chain of the second die in the same predetermined number of clock cycles in which the ATP scan data is loaded into the scan chain of the first circuit die in the hierarchy. Similarly, the pipeline configuration information transmitted to the MCM via the input pin configures the first die output pipeline register 24 of the first circuit die with a reduced delay value to compensate for the scan chain results from the second circuit die traversing the die-to-die interconnect.

[0024] The actual measure of time that is determined can be compared with an expected measure of time to determine whether any defects may exist within the DUT and, for example, within the inter-die wires or connections between inter-die wires and the dies. The die-to-die interconnect between the first die and the second die of the MCM 10 loads the ATP data into the second die scan chain register in the same predetermined number of clock cycles as when the ATP data is loaded into the first die scan chain register. This can result in more accurate at-speed path delay testing. At-speed testing can be particularly important with respect to high-speed devices where quantities such as signal propagation delay and resistance can vary significantly with increases in frequency. The test signals are thus propagated throughout the IC structure at-speed as opposed to at much lower speeds. Multi die testing in a packaged device is achieved looking at the whole packaged device and targeting each die under test by enabling and interconnecting pipeline stages in multiple tiles wherein the interconnected pipeline stages have individually configurable delayvalues depending on the di configured under test.

[0025] FIGs. 6A and 6B shows homogenous circuit dies 12, 14, respectively of a MCM, in accordance with some embodiments. The circuit dies 12 and 14 each have respectively reconfigurable input pipeline registers 22 and output pipeline registers 24, with a die-to-die interface interconnecting the input and output pipeline stages. In some embodiments, test equipment is connected to an input pin of the MCM. The test equipment transmits pipeline delay configuration data for a first die under test (DUT) to configure a first die input pipeline register 22 with a first delay value. The test equipment transmits the ATP data into a targeted die scan chain register on the first die in a predetermined number of clock cycles via the first delay value of the first die pipeline register. The first die is configured to perform a scan chain test of the with the ATP data. The test equipment transmits pipeline delay configuration data for a second DUT to configure the first die input pipeline register 22 with a second delay value, and transmits the ATP data into a second die scan chain register in the predetermined number of clock cycles via the reconfigured first die input pipeline register and the die-to-die interconnect. In some embodiments, the pipeline delay configuration data further includes data to configure a second die input pipeline register with a third delay value, and the ATP data is transmitted into the second die scan chain register via the second die input pipeline register. In such embodiments, the ATP scan data may propagate through the first die input pipeline register having the first delay value in the same amount of clock cycles as propagating through the first and second die input pipeline registers having the second and third delay values, respectively. ATPG vector testing of the MCM 10 using ATP testing may be used with lossless compression, e.g., 1: 10 compression, in loading and configuring the test data.

[0026] FIG. 7 illustrates a data path for loading ATP data into a first die scan chain register of a MCM having multiple homogenous circuit dies 12, 14, in accordance with some embodiments. The ATP data flow is indicated by arrows. Test equipment is connected to an input pin of the MCM and pipeline delay configuration data for a first DUT is transmitted to MCM to configure a first die input pipeline register with a first delay value, shown in FIG. 7 as two flip-flop stages. The pipeline delay configuration data for the first DUT may include a selection signal for the multiplexer connected to the plurality of output taps of the sequence of flip-flops. The ATP data is transmitted into the first die scan chain register, and the scan chain test is performed on the first die.

[0027] After the scan chain test, the results of the scan chain are shifted into the first die output pipeline register 24. Similar to the first die input pipeline register 22. the first die output pipeline register 24 is configurable to have a variable delay, shown in FIG. 7 as a similar sequence of flipflops. The sequence of flip-flops have a plurality of output taps connected to a multiplexer. The pipeline delay configuration data transmitted into the MCM may similarly configure a selection signal for the multiplexer in the first die pipeline output register 24. In FIG. 7, the multiplexer in the first die pipeline output register 24 selects the output corresponding to a two-flip flop delay value. As described in more detail below, the configurable pipeline output registers in each circuit die may further ensure that the scan chain test results are seen at the output pin of the MCM after the same number of clock cycles, regardless of which circuit die is actively under test.

[0028] FIG. 8 illustrates a data path for loading ATP data into a second die scan chain register, in accordance with some embodiments. Pipeline delay configuration data is transmitted into the MCM via an input pin to configure the first and second input pipeline registers, 22 and 22', respectively. Specifically, the first die input pipeline register 22 is configured with a second delay value corresponding to one pipeline flip-flop delay while second die input pipeline register 22’ is configured with a third delay value corresponding to one pipeline flip-flop delay. It should be noted that as each die is homogenous, each die thus includes input pipeline registers usable for configurable delay. Embodiments herein may extend to MCMs having inter-die interconnects between non-homogenous circuit dies, in which one input pipeline register may have a configurable delay value with delay value settings for a plurality of DUT settings. Similar to FIG. 7, the data path for ATP data through each pipeline flip-flop is indicated by an arrow. As shown, the ATP data is transmitted into the MCM via the input pin. The ATP data propagates through the first and second die input pipeline stages each having one flip-flop of delay. As described above, the shift mode frequency of the clock used by the flip-flops may be associated with the propagation delay between the output of the first die input pipeline register and the input of the second die input pipeline register 22’. Thusly altering the route that the ATP data takes so that the timing is the same regardless of which die is being tested, then the same exact pattern with same exact stored sequence and pattern can be read out from the same memory location of the test equipment, which translates to cost savings.

[0029] Similar to FIG. 7, the first and second circuit dies may contain pipeline output registers 24 and 24', respectively. As described above, the first die pipeline output register 24 has a two flipflop delay while the first circuit die was actively under test. The pipeline delay configuration data for the second DUT may include data to reconfigure the first die pipeline output register 24 to have a less (i.e., one flip-flop delay value), as additional output delay is incurred via the die-to-die interconnect when the second circuit die is actively under test. The pipeline delay configuration data configures the second die pipeline output register 24’ with a one flip-flop delay value. The scan chain results are output from the second die scan chain register into the second die pipeline output register 24’, which outputs the results to the first die pipeline output register 24 via die-to- die interconnect. As described above, the shift frequency is selected to ensure sufficient propagation time over the die-to-die interconnect. The number of flip flops in the above examples is purely illustrative, and should not be considered limiting.

[0030] Addressing ATPG Scan Pattern vector depth by reusing the same pattern set to test all tiles (or same dies) achieves higher ATPG scan shift mode frequency and reduces total test time of testing all tiles during production of packaged device with multiple tiles. Reusing the same pattern set irrespective of which tile is under test saves vector memory, thus lowering the packaged device test costs in production. Furthermore, pipeline stages in each homogenous circuit dies reduces the propagation delay between each successive flip-flop, and increases ATPG shift mode frequency (i.e., higher frequency, a shorter time-period) which in turn reduces the actual time spent to test each device. As described, the test pattern data route facilitates timing which is the same regardless of which die is being tested,

[0031] The same ATP pattern set may be used in each circuit die by configuring the input delay for each pipeline stage based on which tile is actively under test in a multi-tile packaged device, as the number of shift vector cycles from the perspective of the testing equipment is same regardless of which circuit die is currently under test, e.g., if Vector Depth (VD) = 60M Cycles and Shift-Frequency(F) = 10ns; then Time To Test Device(TT) = 60M* 10ns = 600ms, and as follows:

[0032] Additional embodiment case 1: If the scan chain test is for 4 Tiles and the ATP is loaded into each tile using pipeline registers with configurable delays, then VD=60*4 = 240M, F=10ns, TT=2.4Sec;

[0033] Additional embodiment case 2: If the scan chain test is performed for 4 Tiles and the ATP is loaded into the tiles individually without pipeline registers, the shift frequency is reduced which increases the period between clock cycles to 40 ns. In such an embodiment. VD=60*4 = 240M, F=40ns, TT=2.4*4Sec=9.6Sec. The goal is to Increase Shift Frequency (F) and Reuse the Same pattern set for all 4-Tiles in Complex Case.

[0034] In these cases. VD=60M total. F=10ns, TT = 4*60*10=2.4Sec; In the cases above, VD=60M which is independent of tiles. In case 1, the shift frequency F=10ns, as compared to Case2 above, which in which F = 40ns, because of the pipeline register stages.

[0035] In a further exemplary embodiment, one may utilize 4-tiles in a packaged device, thus by targeting to test a block with 500 as the scan chain length inside the design (tile). Adding 4 pipeline flops for the Scan-Data-in and 4 pipelines (PL) in Scan-Data-Out before shifting in/out scan data to the block under test in a tile which helps to accelerate scan shift mode frequency, where testing a block in a tile takes 500+4+4=508 as the length; 500 flops are coming from scan chain of the block under test, 4 flops coming in Scan data-in path, 4 flops in Scan-Data out path. The goal is to increase the shift mode frequency which is limited by I/O delay + routing delays in Scan-Data-in/out paths. By enabling pipelines stages one can overcome that and can increase the shift mode frequency. By assuming one pipeline minimum in each tile in scan-Data-in/out path helps to increase the frequency of shift mode ATPG patterns, one can look at the solution as follows. - 4(PL/TileO) + 500(Tile0 block under test) + 4(PL/TileO) => to test block in TileO = Length (508 i.e. 508 vector cycles per pattern) - l(PL/TileO) + 3 (PL/Tilel) + 500 (Tilel block under test-same block as above but different die) + 3 (PL/Tilel) + l(PLZTileO) => to test same block in Tilel = Length (508) - l(PL/Tile0) + 1 (PL/Tilel) + 2 (PL/Tile2) + 500 (Tile2 block under test-same block as above but different die) + 2 (PL/Tile2)+ 1 (PL/Tilel) + l(PL/Tile0) => to test same block in Tile2 = Length (508) - l(PL/Tile0) + 1 (PL/Tilel) + 1 (PL/Tile2) + 1 (PL/Tile3) + 500 (Tile2 block under test-same block as above but different die) + 1 (PL/Tile3) + 1 (PL/Tile2)+ 1 (PL/Tilel) + l(PL/Tile0) => to test same block in Tile2 = Length (508). By configuring mux and pipeline stages in each tile based on the tile which is under test before applying the ATPG patterns (which is large volume vector cycles), one may utilize use the same ATPG pattern set, and reduce shift-in/out time (high frequency of shift clock) since one can safely transfer the shift- data-in/out which in turn effects total test time. In the above example, to test one block in a tile it takes 508 * 10000 (i.e., pattern) * 10ns (=shift mode frequency) = 508 ms, where the total test time depends on shift mode frequency. Embodiments described herein further reduce testing costs by re-utilizing the same ATPG patterns across the various homogeneous tiles.

[0036] One or more embodiments disclosed within this specification can be embodied in other forms without departing from the spirit or essential attributes thereof. Accordingly, reference should be made to the following claims, rather than to the foregoing specification, as indicating the scope of the one or more embodiments. One or more embodiments can be realized in hardware or a combination of hardware and software. One or more embodiments can be realized in a centralized fashion in one system or in a distributed fashion where different elements are spread across several interconnected systems. Any kind of data processing system or other apparatus adapted for carrying out at least a portion of the methods described herein is suited. It should be appreciated, however, that the one or more embodiments are merely exemplary. Therefore, specific structural and functional details disclosed within this specification are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the one or more embodiments in virtually any appropriately detailed structure. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the one or more embodiments disclosed herein.