Testing of a circuit that has an asynchronous timing circuit

The invention relates to testing of an asynchronously controlled circuit, and to a test prepared circuit with an asynchronously timing circuit with provisions to perform testing.

Testability is an essential property of large electronic circuits. Synchronously clocked circuits are conventionally made testable by means of scan chain technology.

Synchronous circuits contain registers that periodically capture output data that is produced by combinatorial logic circuits on the basis of input data from these registers. Scan chain technology couples the registers of the circuit under test in a shift register structure (the "scan chain") during testing. The scan chain makes it possible to control the input signals of the combinatorial logic circuits with test signals and to capture the response of these combinatorial logic circuits to the test signals. The captured response is used to determine whether the circuit contains defects.

The application of scan chain technology to asynchronous circuits presents additional problems. An asynchronous circuit has a timing circuit that determines when respective registers (e.g. edge sensitive registers such as flip-flops or level sensitive registers such as latches) that are connected to the combinatorial logic operate to capture data. The timing circuit of the asynchronous circuit typically contains many logic circuits connected in an application dependent structure to adapt the generation of a timing signal in response to dynamic conditions individually for different registers to which the timing signals are applied. During testing these adaptive timing signals generally have to be replaced by more rigid timing signals from a central clock. When this is done the combinatorial circuits between the registers can be tested in the same way as in the case of combinatorial circuits. However, in the case of an asynchronous circuit the timing circuit should be tested as well. This circuit lends itself less readily to scan chain testing because it does not have the conventional register-combinatorial logic structure of the data circuit. One way of making the timing circuit amenable to scan chain testing is to make it look like a data circuit, by inserting master-slave latch pairs into the timing circuit for test purposes and to connect these latch pairs in the scan shift register structure. During normal operation the latches are made transparent to realize asynchronous operation, but during testing the latches operate as

registers. Effectively, this gives the timing circuit the same type of register/combinatorial logic structure as the data circuit. In this way it is made possible to control signals in the timing circuit with test signals and to observe the response of combinatorial logic circuits in the timing circuit. Although this technique in principle provides a solution to testing of the timing part of an asynchronous circuit, particular attention should be paid to time-continuous feedback loops in the timing circuit. Such loops are typically used to implement asynchronous state machines, which are designed to assume a series of successive states, with state transitions determined by predetermined signal configurations. A time-continuous feedback loop in a digital circuit has the effect that it introduces a dependence of the output signals on preceding input signal changes. This is undesirable for test purposes, because it prevents that there is a one to one relation between test input signals and output signals of correctly operating circuits. Previous transitory signal configurations (glitches) during the application of test signals may affect the output signals. Conventionally it is prevented that this occurs during testing by ensuring that master-slave latch pairs from the scan shift register structure are inserted in each time- continuous feedback loop of the timing circuit. When the master-slave latch pairs are put in a non-transparent state during testing, the time-continuous feedback loops are broken up, which ensures that the output signals will not depend on previous transitory signal configurations. As a result predictable test responses are ensured.

However, the addition of latches in the timing circuit slows down the circuit. The delay introduced by the additional latches in the asynchronous timing circuit is entirely overhead, because these latches have no function during operation. This may be contrasted with the registers in the data part of the circuits, which are used both during testing and normal operation, so that they do not constitute overhead.

WO 2006/013524-A1 describes a test prepared circuit wherein a time- continuous feedback loop is first broken up and then temporarily restored during testing, to capture data determined by the feedback loop. Before restoration of the time-continuous feedback a multiplexer is used to apply loop test data to a feedback input of the time- continuous feedback loop. The multiplexer restores the time-continuous feedback loop during testing after loop-external input signals of the loop, which are determined by test data, have stabilized. This prevents unpredictable history dependent output signals. Because this makes it possible to perform testing with a restored time-continuous feedback loop there is no need to include latches in the feedback loop, which means that static latches can be used in the

scan shift register structure outside the loop to supply and capture test data without affecting the delay of the asynchronous timing circuit.

When testing a time-continuous feedback loop, such as a C-element in the known method it should be avoided that its input signal changes at the same time as the scan enable signal that controls the closing of the loop of the C-element during testing. In the known way of testing this is solved by adding an additional multiplexer in the signal path from the terminal that causes the change in input signal and the input of the C-element. Furthermore this multiplexer is controlled by an additional scan enable signal that changes of state at another point in time than the scan enable that controls the loop of the C-element. It is unavoidable that the addition of test circuitry to functional circuitry in order to make it testable leads to an increased usage of chip area. The additional used area is no longer available to other functions. It would be desirable however if the overhead due to test circuitry could be reduced.

It is therefore a purpose of the invention to provide a method of testing a test prepared circuit that allows for a reduction of test circuit components.

It is a further purpose of the invention to provide a test prepared circuit having a reduced number of test circuit components.

In accordance with the present invention a method of testing a test prepared circuit is provided as claimed in claim 1 and a test prepared circuit is provided as claimed in claim 2.

It was recognized by the inventor that the amount of test circuitry could be reduced by changing the way of timing the testing procedure. According to this insight the test cycle is extended with an additional phase. Each test phases may coincide with a clock cycle, but this is not necessary. More in particular, in a first phase of the test cycle, when the time-continuous feedback loop is broken, test data from a register in the shift register structure is substituted for a feedback signal. During this phase of the test cycle a further test signal is provided to the further logic circuit that is allowed to change the value of the further signal provided by said further logic circuit. A new second phase is added to the test cycle, wherein the further test signal is prevented from changing the further signal provided by said further logic circuit. In this way the output of the further logic circuit is stabilized while the time continuous feed-back loop is maintained open. A separate signal, for example a global signal may prevent the further test

signal from changing the further signal. Otherwise the further test signal itself may assume a value that makes it incapable of changing the further signal.

In a third phase of said test cycle, the time-continuous feedback loop is restored and a test result determined by the feedback loop is captured for transport through the shift register structure.

Due to the fact that an additional phase is inserted into the test cycle, it is not necessary to use an additional multiplexer to prevent a signal transition at the moment of closing the time continuous feedback loop.

In particular this makes it possible to eliminate multiplexers in a latch controller. Therein the further signal is a latch control signal, and the asynchronous timing circuit comprises a further multiplexer for providing the latch control signal. The multiplexer is controlled by a separate stabilization signal. The multiplexer provides an external clock signal (elk) as the latch control signal when the stabilization signal (stab) is deactivated and provides an control signal internally generated in the timing circuit as the latch control signal when the stabilization signal (stab) is activated. In this way the stabilization signal prevents the further test signal elk from changing the further signal. As such latch controllers may occur a large plurality of times in the device under test the elemination of multiplexers therein provides for a considerable saving of circuit area.

The invention can also be applied advantageously in a situation where a time continuous feedback loop has an input directly or indirectly controlled by an arbiter module for arbitrating between requests received at a first and a second input. In that case one of said inputs is coupled to a combinatorial gate for providing either a delayed output signal to said input or a signal having a predetermined value dependent on the value of the further test signal. Here, during the second and third phase of the test cycle the further test signal assumes a value that makes it incapable of changing the further signal.

It is not essential for the present invention whether the various test signals are all provided by an external test apparatus, or whether they are partly or all generated inside the device under test. However it is favorable if the test control circuit in the circuit under test comprises a signal conversion unit for generating derived test signals from a primary test signal and a clock signal. This makes it possible to test the device under test with a conventional testing apparatus. The overhead of this signal conversion module is modest as compared to the gain in circuit area obtained by avoiding multiplexers in the test circuitry.

These and other objects and advantageous aspects of the invention will be described in more detail using non-limiting examples by reference to the following figures.

Figure 1 illustrates a circuit organization

Figure 2 illustrates a register cell Figure 3 shows a typical component of an asynchronous timing circuit

Figure 4 shows a test-prepared component of an asynchronous timing circuit Figure 4A shows an alternative test-prepared component of an asynchronous timing circuit

Figure 5 shows a conventional way of timing a test procedure

Figure 6 shows a first circuit part in a conventional circuit Figure 7 shows a second circuit part in a conventional circuit

Figure 8 shows a method of timing a test procedure according to the invention

Figure 9 shows a first circuit part in a test prepared circuit according to the invention

Figure 10 shows a second circuit part in a test prepared circuit according to the invention

Figure 11 shows a signal conversion circuit in a test prepared circuit according to the invention

Figure 12 shows various signals occurring in the circuit of Figure 11.

Figure 1 illustrates an organization of a typical digital circuit. The circuit contains combinatorial logic circuitry 10, registers 12, a timing circuit 14 and a test control circuit 16. Timing circuit 14 has an input interface 14a and an output interface 14b and outputs coupled to the registers 12. Inputs and outputs of the combinatorial logic circuitry 10 are coupled to the registers 12. Some of the registers 12 also have inputs or outputs coupled to external terminals. Furthermore, registers 12 are connected in series with each other and part of timing circuit 14 in a scan shift register structure. Test control circuit 16 has control outputs coupled to registers 12 and timing circuit 14 (coupling not shown explicitly).

In operation combinatorial logic circuitry 10 uses digital input signals to form digital output signals. The input signals are supplied from outputs of registers 12 to combinatorial logic circuitry 10 and the output signals from combinatorial logic circuitry 10 are received at inputs of registers 12. At points in time controlled by timing circuit 14 the output signals are copied into registers 12, after which the output signals are supplied as new input signals to combinatorial logic circuitry 10.

Although combinatorial logic circuitry 10 is shown as a single box, it should be understood that this box might stand for a collection of many such separate logic circuits. Similarly, although registers 12 are shown in a row, it should be understood in normal operation respective ones of the registers function as registers between successive logic circuits. The presentation of the figure with one box of combinatorial circuits and a row of registers has merely been chosen for explanatory purposes, not to represent the operational function.

The circuit of figure 1 is designed to support a test mode. In the test mode, test control circuit 16 sends control signals to registers 12 to function as a shift register, so that test input and output data can be shifted into and out of the circuit through the chain.

Moreover, when the test input data is at a selected position in the chain, test control circuit 16 can control registers 12 to capture the output signals that combinatorial logic circuitry 10 produce in response to test input data from combinatorial logic circuitry 10.

Figure 2 shows a conventional embodiment of a register 12 for use in the circuit of figure 1. The register contains a multiplexer 120, and a first and second latch 122, 124. An input of the register for a signal from combinatorial logic circuitry 10 (not shown) is coupled to a first input of multiplexer 120, which has an output coupled to a data input of first latch 122. First latch 122 has an output coupled to second latch 124, which in turn has an output coupled to combinatorial logic circuitry 10 (not shown). A second input of multiplexer 120 is coupled to the output of a preceding register 12 (not shown) in the scan shift structure. During normal operation, test control circuit 16 controls multiplexer 120 to pass signals from combinatorial logic circuitry 10 (not shown). Timing signals at timing inputs of latches 122, 124 are used to capture data from a part of the combinatorial logic circuitry 10 and to pass captured data to other parts of the combinatorial logic circuitry 10. In the test mode test control circuit 16 first controls multiplexer 120 to pass data from its second input, that is, from the output of a preceding register in the scan shift register structure. This allows test data to be shifted in. When the test data has reached a position from where it should be used by combinatorial logic circuitry 10, test control circuit 16 sets multiplexer 120 to pass data from combinatorial logic circuitry 10. This enables first latch 122 to capture a response to test input data from combinatorial logic circuitry 10.

Combinatorial logic circuitry 10 forms this response by applying logic operations to test data from any one of the registers 12. The circuitry is said to be combinatorial because its output signals, once stabilized do not depend on previous transitory signal configurations. After the

response has been captured test control circuit 16 controls multiplexer 120 to pass data from its second input, so that the test results can be shifted out.

The circuit of figure 1 is an asynchronous circuit, which means that timing circuit 14 has the capability to adapt the time differences between the points in time at which timing circuit 14 makes different registers 12 capture output signals from combinatorial logic circuits 10, dependent for example on timing signals received from input interface 14a or output interface 14b and/or on internal delays.

An asynchronous timing circuit 14 differs from a synchronous timing circuit. In a synchronous timing circuit the points in time at which registers capture data are defined by a central clock, which has a clock frequency that ensures sufficient delay between successive capture operations. In an asynchronous circuit the points in time are selected as a result of logic operations on timing signals from different sources, as well as transitory state information that is stored in the timing circuit. Many different forms of asynchronous timing circuits for this purpose are known per se. During testing, the selection of points of time is typically performed using a test clock. For this purpose multiplexers (not shown) are typically added at the timing control inputs of registers 12, to replace asynchronous timing signals by test clock signals. This addresses testing of combinatorial logic circuitry 10.

However, the internal components in timing circuit 14 should preferably be tested as well. Figure 3 shows a typical structure of a component 20 of an asynchronous timing circuit 14. The component contains a first combinatorial logic circuit 21 that is used in feed forward fashion and a second combinatorial logic circuit 22 of which an output 24 has a feedback connection 26 to one of its inputs. The inputs of first combinatorial circuit 21 typically derive from the output of components (not shown) that have a similar structure as the component 20. In this example first combinatorial logic circuit 21 has two inputs and two outputs and second combinatorial circuit 22 has three inputs a, b, c, (one of which serves as feedback input) and one output, but of course in other examples other numbers of inputs and outputs may occur.

The combination of second combinatorial circuit 22 and its feedback 26 is called a C-element. The logic function of the second combinatorial logic circuit 22 is designed so that the feedback can be used to lock the C-element into a state that depends on previous input signal values. The values of the input signals (a, b) of second combinatorial logic circuit 22 may be distinguished into different categories: set signal values, reset signal values and retention signal values. When the input signals (a, b) assume a set value this

causes the signal at output 24 to assume a first value. When the input signals (a, b) assume a reset value this causes the signal at the output 24 to assume a second value. When the input signals (a, b) assume a retention value this causes the signal at the output 24 to retain its previous value, whatever that value may be. In a simple example, the second combinatorial circuit 22 may contain a latch comprised of a first and second NAND gate (not shown), the first NAND gate having a first input coupled to the c-input of second combinatorial circuit 22, and an output coupled to a first input of the second NAND gate, which has an output coupled to the output 24 of second combinatorial circuit 22. In this case inputs a, b of second combinatorial circuit 22 may be coupled to second inputs of the NAND gates respectively. In practice, however, second combinatorial circuit 22 will usually involve more complicated logic functions of its inputs.

Figure 4 shows a modified version of the component 20 of figure 3, which has been modified to support testing. A multiplexer 30 has been added at the output of second combinatorial logic circuit 22. In addition to component 20 a first and second register 31, 32 that form part of the scan shift register structure are shown. Multiplexer 30 has a first input coupled to an output of second combinatorial logic circuit 22, a second input coupled to an output of the first register 31, an output coupled to output 24 and feedback 26 and a control input se coupled to test control circuit 16 (not shown).

In operation, in the normal operation mode (when the circuit is not tested) test control circuit 16 (not shown) controls multiplexer 30 to pass the signals from its first input to its output. As a result, component 20 functions in the same way as the circuit of figure 3, with a slightly increased delay due to the added multiplexer 30.

In the test mode test input data is first shifted in via the scan shift register structure. During this shift phase, test control circuit 16 (not shown) sets the control signal se at the control input of multiplexer 30 so that multiplexer 30 passes the signal from first register 31 to the output of multiplexer 30. In this way only multiplexer 30 is functionally inserted in the scan shift register structure.

Subsequently, component 20 is tested. Initially test control circuit 16 (not shown) keeps the control signal se at a value so that multiplexer 30 passes the signal from first register 31 to the output of multiplexer 30. That is, the feedback loop is initially kept broken up. Test input signals are applied to component 20, via other components (not shown) of the timing circuit to the inputs of first combinatorial circuit 21. Because multiplexer 30 keeps the feedback loop broken up at this stage the output signal of second combinatorial logic circuit 22 does not depend on transitory previous signal configurations at its inputs.

Next, once the input signals of second combinatorial logic circuit 22 have stabilized, test control circuit 16 changes the control signal se so that multiplexer 30 passes the signal from its first input, that is, from the output of second combinatorial circuit 22. In this way, the feedback loop is restored. If signals a,b have a set or reset value, the signal at the output of second combinatorial circuit 22 will retain the set or reset value respectively and the output signal of multiplexer 30 will assume this value. If signals a, b do not have the set or reset value, the signal at the output of second combinatorial circuit 22 will retain its previous value, i.e. the value previously defined by the signal at the second input of multiplexer 30. Hence, the output signal of multiplexer 30 will also retain its previous value. During this phase wherein the feedback loop is restored in the test procedure, a clock level change at second register 32 causes the output signal of multiplexer 30 to be captured in second register 32.

Subsequently test control circuit 16 sets the control signal se of multiplexer 30 so that multiplexer 30 passes the signal from its second input to its output. This restores the scan shift register structure to its shift register function. Now the test output data is shifted through the scan shift register structure.

Although switching of multiplexer 30 to pass signals from its first input temporarily creates a feedback loop, this loop does not result in any dependence on unpredictable transitory signal configurations (provided that the circuit functions properly). This is because multiplexer 30 continues to supply a signal from first register 31 , keeping the feedback loop broken until the other input of second combinatorial logic circuit have stabilized. The resulting output signal of second combinatorial logic circuit 22 may be a function of a retained previously applied input signal from first register 31 , or a function of its other input signals, can be captured in second register 32 without timing risks. In certain embodiments of timing circuit 14 some of the feedback loops may have negative loop gain, which occurs when there is an uneven number of inversions around these loops. Typically such feedback loops are interlaced with other feedback loops to ensure that these loops stabilize during normal use. However, if during testing such a feedback loop with negative loop gain would be restored on its own, while the stabilizing loops remain broken, this may prevent the restored feedback loop from stabilizing to a definite state. In such a timing circuit additional test circuitry is preferably provided for specifically for loops with negative loop gain to make it possible to test these feedback loops without restoring the loop.

Figure 4 A shows an alternative modified version of the component 20 of figure 3, which has been modified to support testing loops with a negative feedback- loop. A multiplexer 30 has been added at the output of second combinatorial logic circuit 22. In addition to component 20 a first and second register 31, 32 that form part of the scan shift register structure are shown. Multiplexer 30 has a first input coupled to an output of second combinatorial logic circuit 22, a second input coupled to an output of the first register 31, an output coupled to output 24 and feedback 26 and a control inputs se-1, se-2 coupled to test control circuit 16 (not shown).

In operation, in the normal operation mode (when the circuit is not tested) test control circuit 16 (not shown) controls multiplexer 30 to pass the signals from its first input to its output. As a result, component 20 functions in the same way as the circuit of figure 3, with a slightly increased delay due to the added multiplexer 30.

In the test mode test input data is first shifted in via the scan shift register structure. During this shift phase, test control circuit 16 (not shown) sets the control signal se- 1 at the control input of multiplexer 30 so that multiplexer 30 passes the signal from first register 31 to the output of multiplexer 30. In this way only multiplexer 30 is functionally inserted in the scan shift register structure.

Subsequently, component 20 is tested. Initially test control circuit 16 (not shown) keeps the control signal se-1 at a value so that multiplexer 30 passes the signal from first register 31 to the output of multiplexer 30. That is, the feedback loop is initially kept broken up. Test input signals are applied to component 20, via other components (not shown) of the timing circuit to the inputs of first combinatorial circuit 21. Because multiplexer 30 keeps the feedback loop broken up at this stage the output signal of second combinatorial logic circuit 22 does not depend on transitory previous signal configurations at its inputs. Next, once the input signals of second combinatorial logic circuit 22 have stabilized, test control circuit 16 changes the control signal se-1 so that multiplexer 30 passes the signal from its first input, that is, from the output of second combinatorial circuit 22. In this way, the feedback loop is restored. If signals a, b have a set or reset value, the signal at the output of second combinatorial circuit 22 will retain the set or reset value respectively and the output signal of multiplexer 30 will assume this value. If signals a, b do not have the set or reset value, the signal at the output of second combinatorial circuit 22 will retain its previous value, i.e. the value previously defined by the signal at the second input of multiplexer 30. Hence, the output signal of multiplexer 30 will also retain its previous value. During this phase wherein the feedback loop is restored in the test procedure, a clock level

change at second register 32 causes the output signal of multiplexer 30 to be captured in second register 32.

Subsequently test control circuit 16 sets the control signal se-1 of multiplexer 30 so that multiplexer 30 passes the signal from its second input to its output. This restores the scan shift register structure to its shift register function. Now the test output data is shifted through the scan shift register structure.

Although switching of multiplexer 30 to pass signals from its first input temporarily creates a feedback loop, this loop does not result in any dependence on unpredictable transitory signal configurations (provided that the circuit functions properly). This is because multiplexer 30 continues to supply a signal from first register 31, keeping the feedback loop broken until the other input of second combinatorial logic circuit have stabilized. The resulting output signal of second combinatorial logic circuit 22 may be a function of a retained previously applied input signal from first register 31 , or a function of its other input signals, can be captured in second register 32 without timing risks. The differences with the use of the circuit of figure 2 should be noted. First of all, of course, the circuit of figure 4 concerns part of the timing circuit 14, whereas the circuit of figure 2 is used for capturing test output data from the combinatorial logic circuit 10 that is used for data. Moreover, the circuit of figure 2 is applied to feed forward circuits only; these circuits do not contain feedback paths in conventional scan test practice. In contrast, in figure 4 the component under test contains a feedback loop that results in retention of state information. However, in the particular case of C-elements this does not lead to any problems, because the feedback is broken until all its input signals but its feedback signal have stabilized.

The above described test method requires that the functional inputs of a C- element under test are stable during the observation of that element. This implies that two of these testable C-elements that are connected in series cannot be operated by the same scan enable signal. The switching of the scan enable signal may result in an output transition, which can feed to the functional inputs of subsequent testable C-elements. For this reason, multiple control signals are required to drive the multiplexers, such that no multiplexer is controlled by the same signal as a multiplexer directly in front of it (e.g. a multiplexer that controls an input of the C-element). In practice up to a dozen control signals might be required.

All multiplexer-based C-elements that are not tested during a particular test are kept in scan mode. This means that their state is controlled by the output of a storage element in the scan chain.

Figure 5 shows a timing diagram of test signals in a conventional test procedure. In the first primary data signal PI is offered to the input of the scan chain. The data signal PI is maintained stable during this phase. At a point in time between the beginning and the end of this phase, usually halfway this phase, a clock signal CIk is provided to shift the data in the scan chain. During this phase a scan enable signal se selects the control mode, so that the test data from a register in the shift register structure substitutes the feedback signal

As the clock signal CIk is provided approximately halfway the first phase, the output signal of the register provided to the testable component is stable at the onset of the capture cycle (when the observation takes place). During the capture cycle the signal scan enable se selects the observe mode, so that the response of the testable component to the test data can be observed. A clock signal is provided again substantially halfway this second phase. At that point in time the output of the register in the scan-chain is stable and remains stable until the result is captured. This means that the output of a scan-chain register fulfills the stability requirements and that it can be directly connected to the input of a multiplexer- based C-element. Situations may occur wherein measures need to be taken to prevent the occurrence of unstable signals during test, i.e. signals that can change during the observation of a scan element. The use of multiple scan enables ensures that most of the signals are indeed stable. The following situations however still can lead to unstable signals.

Circuitry driven by the outputs of a latch controller (clock multiplexers) Circuitry driven by an output of an arbitrator.

The state of these circuits can change at the same time the scan enable changes. It is therefore not allowed to directly provide signals of such circuits to the functional inputs of a C-element. To avoid invalidation of the test these signals have to be stabilized during test. A first situation is shown in Figure 6. Figure 6 shows a part 141 of an asynchronous timing circuit 14. The part shown provides a latch control signal LC to control latches 101 in a data path. For clarity only one latch 101 is shown. However one control signal LC may be used to control a plurality of n latches, e.g. 32 in a 32 bit wide data-path. In that case a clock buffer 102 is used in the control signal path for LC. For functional reasons,

there is a feedback from the clock source LC that into the asynchronous timing circuit. There a C-element 142 may receive an input signal a dependent on the feedback signal FB via a signal path 143.

In order to controllably clock the latches 101 during scan a clock multiplexer 103 is inserted for each latch controller (clock buffer). These latches may have both a function during normal operation of the device, as being used in a scan chain during test. These multiplexers 103 select their output signal from the control signal LC generated by part 141 of the asynchronous timing circuit 14 and from a global clock signal CIk used for test purposes. In this way the global clock CIk is provided to all registers 101 during test. To be able to test the C-element 142, the clock multiplexer 103 has to be switched to the "0" state, wherein it selects the control signal LC from the asynchronous timing circuit during the capture. However, switching the clock multiplexer 103 can result in a transition on its output, which means that the output of the clock multiplexer 103 is an unstable signal. To stabilize this signal, conventionally An additional test multiplexer 104 is inserted in the path between the clock multiplexer and the C-element 142 as shown in Figure 6. The two multiplexers 103, 104 are connected to the same scan enable se-1. When the test multiplexer 104 is tested, its input has to be able to propagate through the clock multiplexer 103.

A further situation is shown in Figure 7. In this case the C-element 142 receives an input signal a determined an arbiter 145 via a signal path 143. The arbiter 145 is made predictable by the addition of a controllable delay element 146, here a NOR-gate, in the signal path to one of its inputs 145-1. The arbiter 145 is tested by forcing it in a known state during scan shifting. I.e. the scan enable signal se-1 is asserted so that the NOR-gate provides a logically low output signal to the input 145-1. When the scan enable se-1 is lowered, the arbiter 145 is released and can potentially have a transition on its qa output. Conventionally this output is stabilized by inserting an additional test multiplexer 144.

Figure 8 shows a method of timing a test procedure according to the invention. Therein CIk is the clock signal used to propagate data in the scan chain. PI represents primary input data provided by the test apparatus. The signal stab is a global signal used to stabilize further logic circuits and se is a scan enable signal. Although only one scan enable signal se is shown, a plurality of such signals may be applied in practice.

In a first phase (phase 1) of the test cycle, the scan enable signal se is asserted, so that the time-continuous feedback loop is broken and test data from a register in the shift register structure is substituted for a feedback signal. During this first phase a further test

signal is provided to the further logic circuit. Said further test signal is allowed to change the value of the further signal provided by said further logic circuit.

In a second phase (phase 2) of the test cycle the output of the further logic circuit is stabilized by preventing said test signal from changing the further signal provided by said further logic circuit while still breaking the time continuous feed-back loop.

In a third phase (phase 3) of said test cycle, the time-continuous feedback loop is restored and a test result determined by the feedback loop is captured for transport through the shift register structure. The output of the further logic circuit is maintained stabilized. After phase 3 a new test cycle starts with phase 1. An arbitrary number may be started, depending on a length of the scan chain.

Now it is illustrated by way of example how this method of testing the test prepared circuit allows for a reduction in test circuitry components.

Figure 9 shows a latch controller in a testable circuit of the invention. In Figure 9 parts corresponding to those of Figure 6 have the same reference numerals. In the latch controller of the testable circuit of the invention the clock multiplexer 103 is controlled by the global control signal: stab. During phase 2 and 3 of the test cycle the value of this control signal forces the clock multiplexer 103 to select the source signal LC provided by the asynchronous timing circuit 141, and therewith prevents the signal elk from changing the value of the output signal provided by clock multiplexer 103. Consequently the output signal of the clock-multiplexer 103 is stable when in phase 3 of the test cycle the output signal of C- element 142 is captured. The test multiplexer 104 of Figure 6 is therewith avoided.

Figure 10 shows another example. Parts therein corresponding to those of Figure 7 have the same reference numerals. In phase 1 of the test cycle the stabilization signal stab is deactivated, here maintained high. Now the gate 146 functions as a delay for input signal ar. Consequently in case of a simultaneous change of the signals ar and br, the latter signal determines the state and the output signal qa of the arbitrator 145. In phase 2 the stabilization signal is activated, here maintained high until the end of phase 3. It therewith prevents the output qa of the arbitrator 145 from changing. When in phase 3 the time continuous feedback loop of C-element 142 is closed with signal se, the output signal z of the C-element can be reliably captured in the scan-chain by clock signal CIk. Again the multiplexer 144 of Figure 7 is avoided.

Not all test signals need necessarily be provided by an external test apparatus. Figure 11 shows a conversion module 161 that can be added to the testable circuit. The

conversion module provides a stabilization signal stab, a scan enable signal se and a test clock tck in response to a 'normal' clock signal elk and an externally provided stabilization signal stab provided by the test apparatus.

The conversion module comprises a first edge-sensitive register 162 for generating a sampled version a of the stabilization signal stab. A combinatorial logic gate 163, here an OR-gate provides an intermediate signal b in response to the stabilization signal stab and the sampled version a. A level sensitive register 164 provides the scan enable signal se in response to the intermediate signal b and the clock signal elk. A second combinatorial gate 165, here also an OR-gate is included to provide a clock-gate control signal c from the stabilization signal stab and the sampled version a thereof. This signal c controls a standard clock gating cell 166 that suppresses a clock transition in the test clock tck during the second phase of the test cycle.

Figure 12 more specifically illustrates the operation of the conversion module 161. The test apparatus provides a clock signal elk, and a stabilization signal stab. The stabilization signal stab is maintained inactive (high) during one cycle of the test clock elk and active (low "0") during two subsequent cycles. The transitions in this signal stab are slightly delayed with respect to the transitions in the clock signal elk, in order to prevent a coincidence.

At tO phase 1 begins. During this phase the signal stab is logically high ("1"). Accordingly the output signals c from the logic combinatorial gate 165 is "1", so that the test clock tck follows the clock signal elk provided by the test apparatus. Likewise the output signal b from logic combinatorial gate 163 is "1". This value is latched by the level sensitive register 164 during the first part of phase 1, so that the scan enable signal se is "1".

At point in time tl the high value of the stabilization signal stab is sampled by edge sensitive register 162, so that the intermediate signal a assumes value "1".

At point in time t2 the stabilization signal stab is asserted by a transition to a logically low value. As the signal a is still "l"the output signal c of logical combinatorial gate 165 assumes value "0", so that it inhibits a transition in the test clock signal tck during phase 2. Logic value "1" of intermediate signal a causes combinatorial gate 163 to provide signal b with value "1". This value is latched by level sensitive register 164 and maintained as the scan enable signal se during the remainder of phase 2.

At point in time t3 the value of the intermediate signal a changes to "0", as the stabilization signal stab is sampled. This transition of the intermediate signal a causes a transition of the signal c to "1" and a transition of signal b to "0". At point in time t4 at the

onset of phase 3 this value "0" of signal b is latched by level sensitive register 164, and provided as the output signal se.

At point in time t6 the value of the stabilization signal stab returns to "1" and a new test cycle starts. It is noted that the invention is not restricted to the use of a single stabilization signal. A plurality of stabilization signals may be used, wherein each next stabilization signal stabilizes a larger part of the circuit under test. For example the first stabilization signal stabilizes a portion of the circuit near the source of the disturbance and the last stabilization signal stabilizes the C-element under test. In this way the second phase is subdivided into a number of sub-phases.

Although the invention has been illustrated by means of specific circuit embodiments it should be realized that the invention is not limited to these embodiments. For example, a strict separation between the combinatorial logic circuits 10 and timing circuit 14 has been shown. This separation applies for example to pipelined circuits, wherein data is logically processed in steps and the data is stored between the steps, at least when predecessor data is processed in a next step. However, the invention is not limited to such a strict separation. In other examples the timing circuit may receive input signals from the combinatorial circuits, for example to introduce data value dependent delays, or to generate timing signals in response to the arrival of a data signal. Furthermore, timing circuit may use interactive signal exchanges, such as handshakes wherein timing circuit 14 sends or receives request or acknowledge signals.

Furthermore, although for the sake of simplicity a single shift register structure has been shown, it should be realized that more complicated structures, containing more shift registers, or shift registers with branching or converging shift paths may of course be used. Also, where the use of multiplexers has been described it should be understood that these multiplexers could be implemented with any circuit that has a multiplex function. This includes a logic circuit with an input output relation that copies data from one data input or another dependent on the value of a control signal on a control data input, a circuit with control signal controlled switches between the output and respective inputs, or tri-state drivers with outputs coupled to a multiplexer output and inputs coupled to the respective inputs, the control signal determining which of the drivers will not be in a high impedance output state.

In each case, the multiplexer function may be integrated with the combinatorial logic circuits that precede the multiplexer, e.g. by using tri-state stages in the

final stage of the preceding combinatorial logic circuit, or by integrating the input output relation of the combinatorial logic circuit with the input output relation that corresponds to multiplexing.

It should be noted that the skilled person is readily capable of finding equivalents for the logic functions described. For example, when reversing the polarity of logic signals, the function of a logic OR may be replaced by a logic AND, and vice versa. It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. Parts of the system may implemented in hardware, software or a combination thereof. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word 'comprising' does not exclude other parts than those mentioned in a claim. The word 'a(n)' preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed general purpose processor. The invention resides in each new feature or combination of features.