Title:
THIN-FILM TRANSISTOR ARRAY
Document Type and Number:
WIPO Patent Application WO/2024/105968
Kind Code:
A1
Abstract:
This thin-film transistor array comprises: a flexible substrate having a surface with insulating properties; and a plurality of thin-film transistors disposed on the flexible substrate. A thin-film transistor comprises: a semiconductor layer; a gate electrode; a gate insulating layer that includes a section sandwiched between the semiconductor layer and the gate electrode in the thickness direction of the thin-film transistor; and an inter-layer insulating layer constituted from an organic polymer compound and covering the plurality of thin-film transistors. The plurality of thin-film transistors are lined up at intervals when viewed from a viewpoint opposing the surface of the flexible substrate; and the distance between the gate insulating layer of any thin-film transistor and the gate insulating layer of another thin-film transistor adjacent to said thin-film transistor is 5-200 μm inclusive.
Inventors:
ITO MANABU (JP)
IMAMURA CHIHIRO (JP)
ZHANG HONGLI (JP)
IMAMURA CHIHIRO (JP)
ZHANG HONGLI (JP)
Application Number:
PCT/JP2023/031510
Publication Date:
May 23, 2024
Filing Date:
August 30, 2023
Export Citation:
Assignee:
TOPPAN HOLDINGS INC (JP)
International Classes:
H01L29/786; H01L21/312; H01L21/336
Domestic Patent References:
| WO2013183255A1 | 2013-12-12 | |||
| WO2022196684A1 | 2022-09-22 |
Foreign References:
| JP2016136515A | 2016-07-28 | |||
| US20210020077A1 | 2021-01-21 | |||
| US20200343463A1 | 2020-10-29 |
Attorney, Agent or Firm:
ONDA Makoto et al. (JP)
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